Stratix III Device Configuration

Stratix^® III FPGAs support the following configuration schemes:

Serial—To Conserve Pins
- Active Serial (AS)
  - Uses the Stratix III FPGA to control the configuration process and get the configuration data from a serial configuraton (EPCS) device (PDF).
- Passive Serial (PS)
  - Uses an external intelligent host such as a PC or a microprocessor to control the configuration process synchronously and supply the configuration data serially to a Stratix III FPGA.
- JTAG
  - Configures Stratix III FPGAs via the IEEE Standard 1149.1 interface.
Parallel—For Faster Configuration
- Fast Passive Parallel (FPP)
  - Uses an external intelligent host, such as a PC or a microprocessor to control the configuration process synchronously and supply the configuration data in a parallel manner to the Stratix III FPGA.

For Prototyping or Debugging
- Using Altera^® Programming Cables
  - The Quartus^® II programmer supports configuring Stratix III FPGAs directly using PS or JTAG interfaces via Altera programming cables.
In the Field
- Using Serial Configuration Device (PDF)
  - The Stratix III device gets its configuration data from the EPCS device automatically after power up. However, you need to program the EPCS device first.
- MAX Series Configuration Controller Using Flash Memory white paper (PDF)
  - A MAX^® or MAX II CPLD is used as a flash memory configuration controller to configure Altera FPGAs.
  - Source code (ZIP)