Fast Passive Parallel Configuration
To meet the continuously increasing demand for faster configuration times, Stratix® III devices offer fast passive parallel (FPP) configuration. Stratix III devices are designed with the capability of receiving byte-wide configuration data every clock cycle.
Configuration Methods in Fast Passive Parallel Mode
- Using an enhanced configuration (EPC) device
- Using a microprocessor
- Using a MAX® II device as an external host
For more information, please refer to the Configuring Stratix III Devices chapter in the Stratix III Device Handbook.
Embedded Solution
- Configuring the MicroBlasterTM FPP Software Driver white paper (PDF)
- Portable software driver used to configure an FPGA via an FPP interface
- Source code available for porting to an embedded or other platform
Reference Design
- MAX Series Configuration Controller Using Flash Memory white paper (PDF)
- Using a MAX or MAX II device as a configuration controller to configure Altera® FPGAs from flash memory
- Source code in Verilog and VHDL
