Altera Home Page
文档资料 许可
在线购买 下载

  主页   |   产品   |   支持   |   最终市场   |   技术中心   |   教育与活动   |   公司介绍   |   在线购买  
  mySupport   |   器件   |   软件   |   IP   |   设计范例   |   参考设计  

 FPGA
      Stratix IV(E和GX)
      Stratix III
      Stratix II/Stratix II GX
      Stratix/Stratix GX
      Arria GX
      Cyclone III
      Cyclone II
      Cyclone
  
 CPLD
      MAX II
      MAX 3000A
      MAX 7000
  
 ASIC
      HardCopy III
      HardCopy II
      HardCopy Stratix
      HardCopy APEX 20K
  
 下载
      器件管脚列表
      Gerber Files
      IBIS模型
   BSDL/BST
      PCB符号
  
 配置/编程
   配置
   编程
   编程工具
  
 功耗
   功耗管理
      早期功耗估算器
      认证的电源解决方案
  
 I/O
      I/O规格
      特性
      热插拔
  
 PLL与时钟管理
      概要
      PLL基础
      在软件中使用PLL
      Jitter信息
      时钟网络
      术语
  
 封装和板级设计
      封装规格
      热阻
      布局/Socket
      制造
  
 质量与可靠性
      MSL 计算器
      认证
   环境
      PCN & Advisories
   报告
          Reliability Report
          Process Technology
          JEDEC Compliance
  
 失效分析
      概要
      失效分析能力
  

Process Technology Strategy

Altera and Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) have developed a methodology called FabMatch® to ensure process technology is duplicated across all fabs, thereby resulting in identical devices being produced at multiple wafer fabs. The FabMatch approach compares the process, reliability and device performance data on products from two separate facilities to make certain the process technology is duplicated, and that the products have identical electrical and product performance characteristics. The FabMatch program was initiated in 1998, and adapted by TSMC in 2000. Since then, the program has been used with multiple fabs and processes without issue. FabMatch virtually eliminates capacity constraints and enhances manufacturing flexibility.

The process technology from both fabs is matched by replicating both input and output parameters. In-line measurements of the process parameters, such as the gate oxide thickness, interlevel-dielectric (ILD) thickness, poly etch critical dimension, salicide thickness, and all metal layer etch critical dimensions, are taken and compared to make sure they all are within specification limits. Structural cross-sections of the same device built at both fabs are compared to make sure they are physically identical. The electrical parameters are measured and compared. These include: NMOS/PMOS VT and Isat; N+/P+ contact and sheet resistances; N+/P+ poly contact and sheet resistances; metal 1-9 and poly resistances; and via 1-8 resistances.

Process reliability tests are conducted on the devices from both fabs to confirm that the devices meet reliability requirements. The reliability tests include: high temperature operating life (HTOL) test, (125°C junction, 1.8V, 1000 hours); high temperature storage (HTS) test, (150°C, 1000 hours); temperature cycling (TC) test, (Condition B, 1000 cycles); highly accelerated stress test (HAST), ( 130°C, 85 percent relative humidity, 1.7 ATM pressure, 1.5V bias, 96 hours); biased moisture resistance test, (85°C, 85 percent relative humidity, 1000 hours); and an accelerated unbiased moisture resistance test, (130°C, 85 percent relative humidity, 168 hours).

Product performance measurements are taken and compared to demonstrate that devices from both fabs meet the product performance specifications. The parameters measured and compared can include timing path measurements, phase-locked loop (PLL) measurements, and low-voltage differential signaling (LVDS) measurements.

The FabMatch process compares the process technology, reliability, and product performance data to ensure that all critical parameters measured are well within the product acceptance specifications. Based upon such data, a process transfer from one fab to another can be fully qualified by Altera.

  请填写反馈意见
  注册索取最新邮件通知