Glossary of High-Speed Terms

Method of encoding 8-bit data into a 10-bit form to ensure data is constructed of equal 1s and 0s. Used in high-speed clock data recovery (CDR) data transmissions to ensure data transition density, clock integrity, and DC balancing.

Special code or comma transmitted to show start of data in a serial stream. Used by the receiver to re-align the data.

Reduction of signal amplitude that is commonly caused by the length a signal is required to travel.

Graphical representation of bit error rate generated during bit error rate testing. Shape often is similar to a bathtub due to the varying data edge placements used during the test.

Bit error rate. BER can be considered to be the number of bits of error divided by the number of bits received over a given time.

Bit error rate tester. Instrument used to measure bit error rate. Generally consists of a pattern generator and a signal analyzer.

Built-in self test. Circuitry built into the transceiver to allow testability without the need to connect to the outside world.

Bandwidth. Frequency limits to which a system will perform.

Clock Data Recovery. A technique for embedding clock and data into a single signal for the sake of transmission. High-speed serial data require the clocks to be embedded into the data stream to remove skew and jitter issues associated with transmitting separately.

Transceiver circuitry used to align transceiver channels when more than one channel is required to handle a high-speed data interface.

Continuous jitter pattern. IEEE test pattern used in 10-Gbit Ethernet compliance testing.

Selection of commas used in a particular protocol. For example XAUI utilizes /K/, /A/, /R/ & /T/ codes where /K/ indicates lane synchronization, /A/ indicates lane to lane alignment, /R/ indicates skip code, and /T/ indicates terminate.

Unique codes provided within 8b10b encoding for control information. Also known as K characters.

A signal or noise of identical magnitude and phase that appears on both inputs of a differential receiver. This noise can then be removed at the input of the receiver, known as common mode rejection.

Specific measurement points within a circuit. Used during system characterization to show that a signal conforms to specification.

Undesirable signal from one circuit superimposed onto a secondary circuit, caused by mutual inductance or mutual capacitance between the two circuits.

Continuous random pattern. IEEE test pattern used in 10 Gbit Ethernet compliance testing.

Clock recovery unit. Dedicated circuitry used to recover the clock within a CDR-based transmission scheme.

Stream of data encoded to ensure an equal balance of 1 or 0 . 8b10b encoding has been developed to ensure DC balancing.

A method of coupling two different circuits together, allowing them to share both the static DC and varying AC characteristics of a signal.

Duty cycle distortion. Distortion in a waveform seen as a difference between the pulse width for a 1 and 0 signal. Also known as pulse width distortion.

Data-dependant jitter. Jitter caused by pulse spreading due to system bandwidth limitation. Known as DDJ in time domain, or ISI in frequency domain.

Signaling scheme employing two complementary signals (equal and opposite) for every bit transmitted. Differential signaling allows any common noise to be removed by the buffer.

Poor layout of a PCB that causes the effect of an open track for high speed signals resulting in signal reflection. Typical issues include placing vias at right angles or using 90° cornering during track layout.

Deterministic jitter. Reproducible jitter within a given system, under controlled conditions. Also known as bounded jitter.

Dynamic phase alignment. Method of aligning source-synchronous data to a transmitted clock, simplifying PCB layout by reducing skew issues. DPA can support data rates up to 1 Gbps for Stratix^™ GX devices.

Device under test. Describes the system or unit currently being tested.

Electromagnetic interference. Undesirable electromagnetic waves radiating from one circuit to another, causing interference or noise.

Method of boosting the gain of a high frequency signal to compensate for signal attenuation during transmission. Equalization circuitry is generally included within the receiver circuitry.

A superimposed high-speed waveform generated over a number of data cycles, depicting voltage and timing noise associated with a transmission line. The cleaner the eye within the plot, the better the signal.

Fast Fourier transform

Standard laminate used in the construction of PCBs and backplanes.

Momentary noise on the device ground plane causing a 0 signal to erroneously be seen as a 1. Ground bounce is caused by simultaneously switching outputs (SSO).

HP simulation program with integrated circuit emphasis. Analog circuit simulation models used to determine transceiver behavior during system simulation.

I/O buffer information specification. I/O buffer behavioral models used to determine transceiver behavior during system simulation. IBIS models are not suitable for high-speed simulation above 1 Gbps.

K (comma) code data sequence transmitted when data is not present, to maintain clock data synchronization. 8b10b encoding uses K28.5 code for this function.

Function of ensuring that the impedance of the transmitter, the receiver, and the transmission line are identical. Mismatched impedances could result in signal reflections, ringing, overshoot, undershoot, and stairstep waveforms.

Inter-symbol interference. Data corruption caused by residue of a previous signal interfering with the current data. Generally caused by reflections on the line.

International Telecommunications Union Telecommunication Standardization Sector. Telecommunication standards organization.

Just a bunch Of drives. Storage network term for a disk drive or number of disk drives mounted within their own enclosure but without any control processor.

Time delay between the expected signal transition and the actual transition.

Local area network.

Lightning data transport. Low-voltage differential logic standard used within computer-based applications. Renamed to the HyperTransport^™ standard.

Low-voltage differential signaling. High-speed differential I/O interface commonly used in high-speed transceiver applications.

PCB term describing the layout technique used to ensure that high-speed I/O channels have an equivalent track length. Appear as wiggles on a PCB.

Methodologies for jitter specification. Document describing the jitter specification and measurements for a particular protocol that a product must reach before it conforms to the specification.

The coupling of two conductors via an electric field that injects a current onto the quiet line (victim) proportional to the rate of change of voltage on the driven line (aggressor).

The effect of inducing current from a driven line (aggressor) onto a quiet line (victim) by means of an electric field.

The percentage a waveform rises above its upper determined value before setting at the correct value.

Printed circuit board. Insulated sheet covered with a predefined pattern of conductive material, which becomes a circuit when populated with electronic components.

Positive emitter coupled logic. I/O standard based on emitter couple logic, used in high-speed applications due to its quick state switching properties.

Transceiver logic used to identify specific data patterns within the data stream in order to align the data. Can use 8b10b comma codes, A1A2 patterns within SONET data, or user data codes.

Phase-locked loop. A closed-loop frequency-control system based on the phase difference between the input signal and the output signal of a controlled oscillator. PLLs can correct large and small frequency phase discrepancies through rough and fine tuning, respectively.

Pseudo random bit sequence. A telecommunication test sequence exhibiting certain qualities of randomness and autocorrelation. While a PRBS sequence can be used to evaluate a system's performance under random data conditions, it is fully predictable and repeatable.

Method of boosting a data signal to compensate for IR losses introduced by the transmission medium. Pre-emphasis boosts the initial signal when a transition occurs, but will de-emphasize a signal with a run length greater than 1 following the first unit interval.

Pulse width distortion (see DCD).

Transceiver logic used to match received data to internal logic clock. In CDR-based systems, the clock frequencies of the transmitting and receiving devices often do not match. This mismatch can cause the data to transmit at a rate slightly faster or slower than the receiving device can interpret. The rate matcher resolves the frequency differences between the recovered clock and the PLD logic array clock by inserting or deleting removable characters from the data stream, as defined by the transmission protocol, without compromising transmitted data. Also known as clock correction.

The appearance of a previously transmitted signal on the transmission line causing interference with the current signal. Reflections are caused by a poorly terminated or discontinuous transmission line, where the signal energy is not fully absorbed within the receiver and is therefore transmitted back towards the transmitter.

The appearance of signal overshoot and undershoot at the receiver, caused by reflections on the transmission line.

Random jitter. Unpredictable jitter cased by random noise present during edge transitions, originating from poorly designed components or noisy power supplies.

Random pattern. IEEE test pattern used in 10-Gbit Ethernet compliance testing.

Number of unit intervals (UIs) before a transition must occur in order for the clock to be recovered from the data path. Refers to CDR-based transmissions

Pre-arranged transmission encoding scheme used to bit-disperse data in order to provide DC balancing and ensure CDR. Used in SONET/SDH applications.

Serializer/ deserializer. Converts low-speed parallel data from source into high-speed serial data for transmission at the transmitter.
Converts received high-speed serial data into low-speed parallel data at the receiver.

Design techniques used to ensure transmitted data can be successfully interpreted by the receiver within the tolerances of the protocol.

Slow varying jitter, which is often tracked by a PLL. Sinusoidal jitter results from cross coupling of various signals within the system. Also known as Cyclostationary Noise.

Time delay between different bits transmitted at the same time, measured at the receiver.

K (comma) characters used for data alignment. The receiver will remove these characters from a data stream to allow for skew issues between channels or between system clocks. Used for channel alignment and rate matching.

Synchronous optical network. Telecommunication network standard describing the connection of optical systems.

Simultaneous switching outputs. Condition where a number of outputs switch to the same level at the same time. This may result in ground bounce in a non-protected system.

Addition of passive components onto the transmission line to ensure impedance matching between transmitter, receiver, and transmission line.

Telecom Industry Association. Communication standards organization.

The percentage a waveform falls below its lowest determined value before setting at the correct value.

Used as a method of interconnectivity for a multilayer PCB. Constructed using a tin plated hole connected to the tracks requiring connectivity.

Differential output voltage. Describes the peak-to-peak voltage difference between an active low and active high signal voltage level.

Wide area network. A communications network used to connect a number of LANs together.

Similar to jitter. Long-term variation of a digital waveform from its original transmitted state.

10-Gbit attachment unit interface. Describes optional 10G Ethernet connection between physical interface (PHY) and media access control (MAC). Can be used as an alternative to XGMII for chip-to-chip or backplane applications. XAUI provides a four-channel interface operating at 3.125 gigabits per second (Gbps).

10-Gbit media independent interface. Describes 10-Gbps Ethernet interface connection between MAC and PHY. XGMII provides a 74-pin interface operating at 312 Mhz.

10-Gbit sixteen-bit interface. Describes optional 10-Gbps Ethernet interface connection between MAC and PHY. Requires 16 differential lanes operating between 622 and 645 Mbps.