Simulation Models
When designing high-speed interfaces with faster I/O signaling rates, it is important to perform accurate analog simulation of the systems to avoid signal integrity issues and increase the likelihood of successful printed circuit board (PCB) layout. Altera provides both IBIS and SPICE models that accurately represent the devices’ performance to help support this activity.
IBIS modeling is ideal for high-speed signaling provided by general I/O and memory interfacing. At the higher data and signal edge rates generated by the transceivers within Stratix™ GX and Mercury™ devices, SPICE simulation is recommended as these models give a more accurate representation at higher speed. Altera has partnered with a number of the leading simulation and PCB layout vendors to generate models suitable for use in these tools. Altera now distributes SPICE, DML and VHDL_AMS models to support these tools.
Table 1 describes the simulation modes available for Altera® devices today.
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Table 1. Simulation Models |
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Device |
Model |
|---|---|
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Stratix GX |
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Stratix |
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APEX™ II |
|
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Mercury |
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Note
- Now available; contact mySupport for more information
In addition to the standard models, Altera also provides a silicon design in kits for the Cadence Allegro Platform and the Mentor Graphics ICX and Hyperlynx tools. The kits contains validated models, topology files, layout constraints, example PCB files and footprints, tutorials, documentation, scripts, and other utilities. The kit simplifies and speeds system modeling and PCB design.
Links to Partners
Printed Circuit Board Design
Board layout is fundamental to the success of high-speed design. It is important that a number of considerations and rules are observed to ensure complete success. Altera has generated a number of documents and guidelines to aid PCB design and layout. These documents provide information and solutions regarding:
- Ground bounce
- Termination
- Trace layout
- Crosstalk
- Board stacks
- Use of vias in high-speed board layouts
- Grounds return paths
- Decoupling
In addition, the Stratix GX Development Board provides a worked example of how to layout for high-speed design. All documentation, including schematics and Gerber layouts, are available as part of the development kit.
The following documentation provides detailed material to support the PCB designer throughout the design and layout stage of the project.
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Table 2. Layout Material |
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Device |
Available Documentation |
|---|---|
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All Devices |
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|
Stratix GX |
Stratix GX Board Specific Design Guidelines |
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Stratix GX Development Board Schematics (1) |
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Stratix GX Development Board Layout & Assembly Files (1) |
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Note
- Now available; contact your Altera sales representative for more information
I/O Characterization
I/O characterization is an important factor of Altera device conformance testing. The results provide evidence of I/O performance against protocol specification, and provide users with information such as transceiver speed, jitter performance, and power performance. Design engineers can use this information as an indication of expected results during product selection and during compliance testing. The information can also be used for correlating SPICE models to ensure accurate SPICE modeling.
Characterization Reports
Full characterization reports are now available for a number of Altera device families. All reports can be obtained from your local Altera sales representative.
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Table 3. I/O Characterization Reports |
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Device |
Characterization Reports |
|---|---|
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Stratix GX |
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Stratix |
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APEX II |
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Mercury |
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Development Boards
Table 4 provides links to Altera’s high-speed development board portfolio. Extensive documentation is available with all boards, to aid system design and overcome board layout issues.
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Table 4. Development Boards |
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Device |
Documentation |
|---|---|
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Stratix GX |
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Stratix |
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APEX II |
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|
Mercury |
|
Note
- Now available; please contact your Altera sales representative for more information
