Date December 2007
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Design Description: This design includes Cyclone III to x32 read/write DDR2 SDRAM interface

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Quartus Version 7.2 Build 151 
Modelsim Version ModelSim ALTERA 6.1g
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Spec
-> Type of Controller               		: DDR2 SDRAM High Performance Controller 
-> Speed                            		: 167MHz
-> Width                            		: x32
-> F/H Rate                         		: Half rate
-> Latency                          		: 5
-> Burst Length                     		: 4
-> IO Standards                     		: SSTL-18 Class I
-> OCT                              		: None
   -> Signal                        		: None
      -> Type                       		: None
      -> Calibration                		: None
      -> Dynamic                   		: None
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FPGA Device                         		: EP3C120F780C7
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Memory Device                       		: None
-> DIMM
   -> Base Device                   		: None
-> Component                        		: Micron MT47H32M16CC-3 
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Design Name                         		: DDR2
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Design Language                     		: Verilog HDL
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Files (HDL, TCL, SDC ...)
-> DDR2												: DDR2 High Performance Controller MegaWizard PlugIn
	-> DDR2_controller_phy.v								: Top module for phy and memory controller
		-> DDR2_phy									: DDR2 ALTMEMPHY MegaWizard PlugIn
			-> DDR2_phy_alt_mem_phy_ciii.v						: Contains all modules of the ALTMEMPHY variation except for the sequencer
				-> DDR2_phy_alt_mem_phy_addr_cmd_ciii.v				: Generates the address and command structures							
				-> DDR2_phy_alt_mem_phy_clk_reset_ciii.v			: Instantiates PLL, DLL, and reset logic						
					-> DDR2_phy_alt_mem_phy_reset_pipe.v			: Reset and pipeline modules
					-> DDR2_phy_alt_mem_phy_pll_ciii			: PLL MegaWizard PlugIn
				-> DDR2_phy_alt_mem_phy_dp_io_ciii.v				: Generates the DQ, DQS, DM, and QVLD I/O pins
				-> DDR2_phy_alt_mem_phy_mimic.v					: Creates the VT tracking mechanism for DDR3, DDR2, and DDR SDRAM PHYs
				-> DDR2_phy_alt_mem_phy_mux.v					: Differentiates signals between calibration and user mode
				-> DDR2_phy_alt_mem_phy_read_dp_sii_ciii.v			: Takes the data from the pin up to the half-rate I/O registers
				-> DDR2_phy_alt_mem_phy_sequencer_wrapper.v			: A wrapper file that calls the encrypted sequencer file
				-> DDR2_phy_alt_mem_phy_write_dp_sii_ciii.v			: Generates the demultiplexing of data from half-rate to full-rate DDR data
		-> DDR2_auk_ddr_hp_controller_wrapper.v						: A wrapper file that calls the encrypted High performance controller file
-> DDR2_example_driver.v									: Example driver
	-> DDR2_ex_lfsr8.v									: LFSR pattern for self checking on DDR2
-> sld_hub.vhd											: The main component of the SignalTap II Embedded Logic Analyzer, providing the trigger logic and JTAG interface required for debugging
-> sld_signaltap.vhd										: The main component of the SignalTap II Embedded Logic Analyzer, providing the trigger logic and JTAG interface required for debugging
-> DDR2_example_top.v										: Top module for example driver and High Performance Controller
-> DDR2_pin_assignments.tcl									: Adds I/O standard settings for all memory interface pins, and adds output enable group assignments to ensure VREF rules are met when the design contains input/bi-directional pins
-> DDR2_phy_report_timing.tcl									: Generates a detailed timing report for all timing paths in the ALTMEMPHY instance
-> DDR2_phy_ddr_timing.sdc									: Sets timing constraints for the ALTMEMPHY megafunction instance
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Simulation
-> testbench/DDR2_example_top_tb.v              : Design test bench
-> testbench/DDR2_mem_model.v			: DDR2 verilog model
-> simulation/modelsim/vsim.wlf			: Simulation waveform result

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Board                               : Cyclone III GX Development Kit
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Instructions                        : Refer to the Using DDR, DDR2, and DDR3 SDRAM in Arria II GX devices chapter in Volume 6, Section I of the External Memory Interface Handbook

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Contact Altera
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Although we have made every effort to ensure that this design example works correctly, there might be problems that we have not encountered.
If you have a question or problem that is not answered by the information provided in this readme file or the example's documentation, please
contact your Altera Field Applications Engineer. If you have additional questions that are not answered in the documention provided with this
function, please contact Altera Applications:

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