Date 26-JUNE-2010 =============== Demo 400MHz RLDRAMII SDRAM interface in Stratix IV device. =============== Quartus Version 10.0 Modelsim Altera Version 6.5b ================ Spec -> Type of Controller : RLDRAM II Controller with UniPHY v10.0 -> Speed : 400MHz -> Width : x36 single RLDRAMII SDRAM component -> F/H Rate : Half-Rate Controller -> Latency : RL6 -> Burst Length : 4 -> IO Standards : 18 HSTL IO Standard class I -> OCT : -> DQ, QK, DK, DM, and memory clock signals : -> Type : 50 ohms series/50 ohm parallel -> Calibration : Power up -> Dynamic : Yes -> Current strength : -> Command and address signals : Maximum current strength ================ FPGA Device : EP4SE530H35C2 ================ Memory Device : -> DIMM : None -> Base Device : None -> Component : MT49H16M36HT-18 ================ Design Name : rldram_example_top ================ Design Language : Verilog HDL ================ Files (HDL, TCL, SDC ...) : -> hb_emi_rldramii_siv_uniphy.qar : QuartusII v10.0 Complete Archive -> rldram_example_top.v : Top level design -> rldram.v : RLDRAM II controller with Uniphy V10.0 MegaWizard PlugIn. -> rldram_controller_phy.v : Top level file for controller and PHY. -> rldram_alt_rld_controller.sv : Top level module of the RLDRAM II Memory Controller. -> rldram_alt_dqr_afi.sv : The AFI module. -> rldram_memctl_burst_latency_shifter.sv : The burst latency shifter. -> rldram_memctl_data_if.sv : The data interface module controls the Avalon interface by accepting requests when the controller is ready, and putting the Avalon bus into a wait state when the controller is busy by deasserting 'avl_ready'. -> rldram_alt_rld_fsm.sv : The main state machine of the RLDRAM II Memory Controller and it accepts user requests from the Avalon interface as well as issues memory commands while satisfying timing requirements. -> rldram_memphy_top.v : Top level file of UNIPHY, which instantiates the DLL, PLL and PHY. -> rldram_memphy.v : This file instantiates all the main components of the PHY. -> rldram_addr_cmd_datapath.v : This module contains address and command datapath. -> rldram_afi_mux.v : This module contains a set of muxes between the sequencer AFI signals and the controller AFI signals. -> rldram_io_pads.v : Top level file of all I/O pads for PHY. -> rldram_addr_cmd_pads.v : The addr/cmd pad instantiates the I/O logic blocks for address/command. -> rldram_read_pads.v : The read pad instantiates the I/O logic blocks for read data capture. -> rldram_mem_cq_buf.v -> rldram_mem_q_buf.v -> rldram_read_dq_dqs.v -> rldram_write_pads.v : The write pad instantiates the I/O logic blocks for write data. -> rldram_clock_pair_generator_config.v -> rldram_write_mask_iobuf.v -> rldram_write_mask_pad_hr.v -> rldram_write_dq_dqs_hr.v -> rldram_write_d_iobuf.v -> rldram_read_datapath.v : The read datapath is responsible for read data resynchronization from the memory clock domain to the AFI clock domain. -> rldram_flop_mem.v -> rldram_read_valid_selector.v -> rldram_reset.v : This module contains reset module for PHY. -> rldram_reset_sync.v -> rldram_sequencer.sv : The sequencer is responsible for intercepting the AFI interface during the initialization and calibration stages. -> rldram_write_datapath.v : This module contains write datapath. -> rldram_oct_control.v : This module contains parallel termination control, rdn, rup, series termination control. -> rldram_pll_memphy.v : This module contains pll module. -> rldram_dll_memphy.v : this module contains dll module. -> rldram_example_driver.v -> rldram_driver.sv : The Example Driver is a parametrizable Avalon Memory-Mapped Master used to test various memory interfaces. -> rldram_scfifo_wrapper.sv : This module is a wrapper for the scfifo. -> rldram_addr_gen.sv : This module is a wrapper for the address generators. -> rldram_rand_addr_gen.sv : The random address generator generates random addresses and burstcounts within parametrizable ranges. -> rldram_burst_boundary_addr_gen.sv : This module rounds up the input address to the next burst boundary. -> rldram_rand_num_gen.sv : This module provides an uninterrupted stream of random numbers by buffering the output of the random number generator, which may be paused when the LFSR output is not within the specified range. -> rldram_rand_num_gen_unbuffered.sv : The random number generator uses the LFSR module to generate random numbers within a parametrizable range. -> rldram_lfsr.sv : The Pseudo-Random Shift Registers (LFSR) generates 2^n-1 pseudo random numbers where n is the width of the LFSR. -> rldram_rand_burstcount_gen.sv : The random burstcount generator generates random burstcounts within parametrizable ranges. -> rldram_rand_seq_addr_gen.sv : The mixed random/sequential address generator generates addresses within a parametrizable range that are random or sequential with a parametrizable probability. -> rldram_seq_addr_gen.sv : The sequential address generator generates sequential addresses starting with a parametrizable address. -> rldram_template_addr_gen.sv : This is an example address generator, which simply alternate between 0x0 and 0x1. -> rldram_avalon_traffic_gen.sv : The Avalon traffic generator translates the commands issued by the state machine into Avalon signals. -> rldram_lfsr_wrapper.sv : This module is a wrapper for the Linear feedback shift registers (LFSR) module. -> rldram_fsm.sv : The driver state machine controls the test stages modules, and multiplexesthe signals into and out of the active stage module. -> rldram_block_rw_stage.sv : The block write/read test stage performs a parametrizable number of write operations, followed by the same number of read operations to the same addresses. -> rldram_single_rw_stage.sv : The single write/read test stage performs a parametrizable number of interleaving write and read operation. -> rldram_template_stage.sv : This is an example test stage, which issues write and read commands with progressing number of cycles between commands. -> rldram_read_compare.sv : When enabled, the read compare module buffers the write data and compares it with the returned read data. -> sld_signaltap.vhd -> sld_hub.vhd -> rldram_pin_assignments.tcl : Adds I/O standard settings for all memory interface pins, and adds output enable group assignments to ensure VREF rules are met when the design contains input/bi-directional pins. -> rldram_report_timing.tcl : Generates a detailed timing report for all timing paths in the ALTMEMPHY instance. -> rldram.sdc : Sets timing constraints for the ALTMEMPHY megafunction instance. -> rldram_timing.tcl : Contains timing constraints for your UniPHY variation. -> rldram_parameters.tcl -> rldram_map.tcl : Contains the traversal routines that are used by both rldram_plus_pin_assignments.tcl and rldram_plus.sdc scripts. -> rldram_report_timing_core.tcl : Contains timing analysis for read and write paths. -> S3_Demo_RLDRAM_BTModal.tcl : Board Trace Models for SIV & MT49H16M36HT-18 Boards -> S4_Host_RLDRAM_PinLocations.tcl : Pin Location Assignments for SIV E F1152 Developement Board RLDRAMII SDRAM Interface ================ Features (e.g. Advanced IO Planner, DTW ...) -> Advanced IO Timing, Board Trace Models, SignalTapII : Launch SignalTapII, program device, view signals ================ Simulation -> rldram_example_top_tb : Simulation top level test bench file -> rldramii_mem_model.sv : Simulation memory model file ================ Board : Stratix IV E F1152 Development Board ================ Instructions -> Simply Un-archive the QAR and recompile. -> Launch SignalTapII, program device, and view the signals -> Refer to Volume 6, Section II of the External Memory Interface Handbook for fULL design guidelines and flow ================ Contact Altera ================ Although we have made every effort to ensure that this design example works correctly, there might be problems that we have not encountered. If you have a question or problem that is not answered by the information provided in this readme file or the example's documentation, please contact your Altera Field Applications Engineer. If you have additional questions that are not answered in the documention provided with this function, please contact Altera Applications: World-Wide Web: http://www.altera.com http://www.altera.com/support Technical Support Hotline: (800) 800-EPLD (U.S.) (408) 544-7000 (Internationally) Copyright (c) 200910 Altera Corporation. All rights reserved.