CIC Interpolation Filter with Multi-Channel Data Support
The CIC Interpolation Filter with Multi-Channel Data Support design example demonstrates how to use Altera® CIC MegaCore® function to implement digital sample rate up conversion for multiple independent data sources.
Digital signal processing (DSP) systems often need to work with multiple parallel channels. For digital data rate down or up conversion applications (if different channels have identical rate change requirement), instead of duplicating the same hardware for each input channel, time sharing of low rate hardware sections can provide significant resource re-use. This is the concept of multi-channel operation of the Altera Cascaded-Integrator-Comb (CIC) filter MegaCore function.
In this example, we configure the CIC Compiler to support multiple interfaces so we can take advantage of resource saving in the single-input-multiple-output (SIMO) mode for interpolation. The overall system diagram is shown in Figure 1. For more information on CIC multi-channel support, refer to the CIC Compiler User Guide (PDF). For more details of Altera wireless digital up/down conversion solutions, refer to AN 421: Accelerating WiMax DDC & DDC System Designs (PDF).
Figure 1. Block Diagram of Digital Up Conversion example Using CIC Filter in SIMO Mode
Features
This demonstration has the following features:
- The CIC filter is configured to have two independent interfaces to support parallel input data channels. This allows the CIC filter to time share the low data comb filter sections for all input channels.
- Altera finite impulse response (FIR) Compiler is configured to have an inverse sinc frequency response to compensate CIC filter droop.
- The FIR Compiler uses the multi-cycle-variable (MCV) architecture, which re-uses multipliers and provide additional resource saving. For more information on MCV architecture, refer to the FIR Compiler User Guide (PDF).
- A MATLAB script designing CIC compensating filter is provided for your reference. The script uses the frequency sampling method to design a FIR filter that has an inverse sinc frequency response. The overall system response is plotted for you to verify key system specifications such as the pass band ripple and stop band attenuation.
- Altera Avalon® Streaming Interface is used to transfer packet data from multiple data sources between MegaCore functions. For more information about Avalon Streaming Interface, refer to the Avalon Streaming Interface Specification.
- Avalon Streaming Packet Format Converter is included to properly interleave/deinterleave multiple data channels.
Model
The inputs to the design example are two independent data sources. One source signal is a sine wave and the other is a cosine wave. Both have a carrier frequency of 2.5 MHz. Part of the input signal is corrupted by high-frequency additive noise. The data sources generate continuous data; therefore, the startofpacket and endofpacket signals of the Avalon Streaming Interface are configured to indicate streaming data.
The input data sources generate one valid sample every 8 clock cycles, corresponding to an equivalent data rate of 10 MHz and bus utilization at 12.5 percent. The packet format converter interleaves the data sources and the bus utilization is doubled. A FIR filter precludes the CIC filter to provide pre-conditioning to CIC filter frequency droop and also additional up sampling by 2. Its output bus utilization becomes 50 percent. The CIC filter implements the bulk of rate change, in this case up sampling by 4. It is configured to have the SIMO structure, where interleaved input signals time share the comb filter sections as they enter the CIC filter. Two independent output interfaces are generated to split the interleaved multi-channel input data. CIC filter output sampling rate is 80 MHz with 100 percent bus utilization for both output channels. Note that the backpressure of Avalon Streaming Interface in this up conversion chain is not activated and can actually be optimized away. It can be shown that without backpressure, the same functional design can operate at higher speed and use fewer resources at the cost of slightly more complex source signal control. For more information, refer to AN 421: Accelerating WiMax DDC & DDC System Designs (PDF).
Download the files used in this example:
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Parameters
Tables 1 and 2 list the parameter settings used in the interpolation example.
| Table 1. Parameters for CIC Compiler |
| CIC Parameters |
Values |
| Filter Type |
Interpolation
|
| Number of Stages |
4
|
| Rate Change Factor |
4
|
| Differential Delay |
2
|
| Number of Interfaces |
2
|
| Number of Channels Per Interface |
1
|
| Input Data Width |
16
|
| Output Data Width |
16
|
| Hogenauer Pruning |
-
|
| Output Rounding |
Convergent
|
| Table 2. Parameters for FIR Compiler |
| FIR Parameters |
Values |
| Rate Specification |
Interpolation by 2 |
| Input Channels |
2 |
| Input Bitwidth |
Signed Binary 8 |
| Output Bitwidth |
Full Resolution |
| Coefficient Scaling |
None |
| Device Family |
Stratix® II |
| Structure |
MCV |
| Pipeline Level |
2 |
| Data Storage |
M4K |
| Coefficient Storage |
M512 |
| Multiplier |
DSP Blocks |
| Clocks per Output Data |
2 |
| Coefficients Input |
From File |
Related Links
For more information on related features used in this design example in your project, go to:
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
|
文档资料
> 
