Altera Home Page
文档资料 许可
在线购买 下载

  主页   |   产品   |   支持   |   最终市场   |   技术中心   |   教育与活动   |   公司介绍   |   在线购买  
  mySupport   |   器件   |   软件   |   IP   |   设计范例   |   参考设计  

 产品
      MAX/MAX II
      Stratix/Stratix GX
      Nios II
  
 功能
      算法
      存储器
      总线及I/O
      逻辑
      接口与外设
      DSP
      通信
      PLL & Clocking
  
 设计输入方法
      Quartus II软件工程
      Tcl
      VHDL
      Verilog HDL
      C Code 范例
      DSP Builder
      TimeQuest
   片内调试
  
 仿真工具
      Mentor Graphics ModelSim
      Cadence NCsim
      Synopsys VCS
  
 旧范例
      图形编辑器
      AHDL
  

DSP Builder: Complex Multiplier With Reloadable Coefficients Using Canonical Representation

This example describes an 18 x 18 signed complex multiplier design in DSP Builder. The complex multiplier is implemented using distributed arithmetic (DA) which is implemented using the M4K TriMatrix memory blocks. The design example uses the canonical representation for complex multiplication requiring three multipliers, three adders, and two subtractors:

D = Dr + j*Di  { Data }

C = Cr + j*Ci  { Coefficient }

R = D*C = Rr + j*Ri  { Result }

Rr = Dr*Cr – Di*Ci    {same as conventional representation}

Rr = Dr*Cr – Di*Ci + (Dr*Ci - Di*Cr) - (Dr*Ci - Di*Cr)

Rr = (Dr*Cr – Dr*Ci + Di*Cr - Di*Ci) + (Dr*Ci - Di*Cr)

Rr = ((Dr + Di)*(Cr - Ci)) + (Dr*Ci - Di*Cr)

Ri = Dr*Ci + Di*Cr     {same as conventional representation}

The coefficient is implemented as partial products in the M4K TriMatrix memory blocks. The M4K memory blocks are configured as dual-port RAMs and can store two sets of coefficients. To choose which coefficient set to use, set the coef_set bit appropriately. 

The coefficient is also re-loadable while the multiplication operation takes place. It will automatically reload into the coefficient set which is not being used. To reload a new coefficient, assert the coef_reload bit and keep it asserted throughout the entire reload period. The partial product for the coefficient needs to be pre-computed. Refer to the compute_partial_product.m script for details.

Download the files used in this example:

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

Files in the zip download include:

  • complex_mult_C_DA_reloadable_coef_MEM.mdl—DSP Builder design file implementing 18x18 complex multiplier with reloadable coefficients
  • init.m—MATLAB script to initialize the sampling time, simulation time and coefficient value
  • compute_partial_product.m—MATLAB script to calculate the partial products based on the constant coefficient value set in init.m. Two sets of partial products are calculated for each coefficient value: one for the most significant bit (MSB) segment and the other for the least significant bit (LSB) segment of the data
  • complex_mul.m—MATLAB script to verify the simulation results in Simulink

Figure 1 shows the top-level diagram of the complex multiplier design example in DSP Builder.

Figure 1. Signed 18 x 18 Complex Multiplier Top-Level Diagram

Figure 1. Signed 18x18 Complex Multiplier Top-Level Diagram
View Full Size

Table 1 lists the ports and gives a description for each.

Table 1. Signed Complex Multiplier Port Listing
Port Name Type Description
DataInI[17:0], DataInQ[7:0] Input 18-bit data inputs to complex multiplier unit
coef_real_msb[23:0], coef_real_lsb[23:0],

coef_imag_msb[23:0], coef_imag_lsb[23:0]

Input 24-bit partial product inputs based on the coefficient to complex multiplier unit. Used during coefficient reloading.
coef_set Input The M4K memory block stores partial products for two sets of coefficients. This bit selects which set to use for the complex multiplication operation.
coef_reload Input Initiate reloading of coefficient into memory. It overwrites the coefficient set which is not being used (determined by coef_set bit)
ResI[36:0], ResQ[36:0] Output 37-bit data output of complex multiplier unit

Related Links

For more information on related features used in this design example in your project, go to:

Design Examples Disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.

  请填写反馈意见