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主页 > 支持 > 设计范例 > DSP Builder 打印此页 订阅电邮新闻 Altera's DSP Builder Design Examples Table 1 contains digital signal processing (DSP) design examples created in DSP Builder. To see the design example, choose the corresponding icon in the Design Entry Method column. For more information on Altera's DSP Builder, refer to the DSP Builder support page. Table 1. DSP Design Examples—Functions and Design Entry Methods Function Design Entry Method Polyphase Modulation With Aliasing for Digital Up-Conversion Designing Digital Down Conversion Systems Using CIC and FIR Filters Using CIC Decimation Filter With Multi-Channel Support CIC Interpolation Filter With Multi-Channel Data Support Deinterlacer Using Weave Mode Deinterlacer Using Bob Mode Gamma Correction YCbCr to RGB Color Space Conversion Image Frame Resizing Using Scaler Salt and Pepper Noise Removal Using 2D Median Filter Video Picture in Picture (PIP) Mixing Using Alpha Blending Mixer Chroma Resampler Up-Conversion 2D Sharpening Finite Impulse Response (FIR) Filter Viterbi Tail-Biting Double-Pass Decoding (Packet Size = Traceback Length) Viterbi Tail-Biting Double-Pass Decoding (Packet Size = 2 Traceback Length) Viterbi Tail-Biting Triple-Pass Decoding (Packet Size = Traceback Length) Complex Finite Impulse Response (FIR) Filter Bit-Error Rate (BER) Performance Measurement of Viterbi Decoder Half-Band Filter Using Distributed Arithmetic Half-Band Filter Using Distributed Arithmetic & Time Domain Multiplexing (TDM) Half-Band Filter With Reloadable Coefficients Half-Band Filter Using DSP Blocks Complex Multiplier With Reloadable Coefficients Using Conventional Representation Complex Multiplier With Constant Coefficients Using Conventional Representation Complex Multiplier With Variable Coefficients Using Conventional Representation Complex Multiplier With Reloadable Coefficients Using Canonical Representation Complex Multiplier With Constant Coefficients Using Canonical Representation Complex Multiplier With Variable Coefficients Using Canonical Representation The following icons indicate the entry mode(s) used in each example: Altera® hardware description language (AHDL) VHDL MAX+PLUS® II graphic editor Verilog hardware description language (HDL) Tool command language (Tcl) Quartus® II development tool Simulink model Related Links DSP Literature The MathWorks & Altera DSP Design Flow Overview FPGA Design Flow System-Level Design Flows Design Examples Disclaimer These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera. 给本页评分

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