Table 1 contains digital signal processing (DSP) design examples created in DSP Builder. To see the design example, choose the corresponding icon in the Design Entry Method column. For more information on Altera's DSP Builder, refer to the DSP Builder support page.
| Table 1. DSP Design Examples—Functions and Design Entry Methods | |
| Function | Design Entry Method |
|---|---|
Multichannel Farrow Filter |
Simulink Model |
| Sigma-Delta Converter |
Simulink Model |
| Polyphase Modulation With Aliasing for Digital Up-Conversion |
Simulink Model |
Designing Digital Down Conversion Systems Using CIC and FIR Filters |
Simulink Model |
| Using CIC Decimation Filter With Multi-Channel Support | Simulink Model |
| CIC Interpolation Filter With Multi-Channel Data Support | Simulink Model |
| Deinterlacer Using Weave Mode |
Simulink Model |
| Deinterlacer Using Bob Mode |
Simulink Model |
| Gamma Correction |
Simulink Model |
| YCbCr to RGB Color Space Conversion |
Simulink Model |
| Image Frame Resizing Using Scaler |
Simulink Model |
| Salt and Pepper Noise Removal Using 2D Median Filter |
Simulink Model |
| Video Picture in Picture (PIP) Mixing Using Alpha Blending Mixer |
Simulink Model |
| Chroma Resampler Up-Conversion |
Simulink Model |
| 2D Sharpening Finite Impulse Response (FIR) Filter |
Simulink Model |
| Viterbi Tail-Biting Double-Pass Decoding (Packet Size = Traceback Length) | Simulink Model |
| Viterbi Tail-Biting Double-Pass Decoding (Packet Size = 2 Traceback Length) | Simulink Model |
| Viterbi Tail-Biting Triple-Pass Decoding (Packet Size = Traceback Length) | Simulink Model |
| Complex Finite Impulse Response (FIR) Filter | Simulink Model |
| Bit-Error Rate (BER) Performance Measurement of Viterbi Decoder | Simulink Model |
| Half-Band Filter Using Distributed Arithmetic | Simulink Model |
| Half-Band Filter Using Distributed Arithmetic & Time Domain Multiplexing (TDM) | Simulink Model |
| Half-Band Filter With Reloadable Coefficients | Simulink Model |
| Half-Band Filter Using DSP Blocks | Simulink Model |
| Complex Multiplier With Reloadable Coefficients Using Conventional Representation | Simulink Model |
| Complex Multiplier With Constant Coefficients Using Conventional Representation | Simulink Model |
| Complex Multiplier With Variable Coefficients Using Conventional Representation | Simulink Model |
| Complex Multiplier With Reloadable Coefficients Using Canonical Representation | Simulink Model |
| Complex Multiplier With Constant Coefficients Using Canonical Representation | Simulink Model |
| Complex Multiplier With Variable Coefficients Using Canonical Representation | Simulink Model |
Related Links
- DSP Literature
- The MathWorks and Altera
- DSP Design Flow Overview
- FPGA Design Flow
- System-Level Design Flows
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
