Gamma Correction Design Example
The luminance generated by a physical device is usually not a linear function of the applied voltage. Most CRT displays have a power-law transfer characteristic with a gamma of about 2.5. This design example shows how to perform gamma correction using Altera's Gamma Corrector MegaCore® function in DSP Builder to compensate for this nonlinearity effect. You can run-time parameterize the gamma values shown in Table 1 through configuration registers.
The model consists of an image stream source block, a control signals block, a gamma corrector block, and an image stream sink block. The image stream source block reads the input binary file and feeds the data stream to the gamma corrector block. The image stream sink block writes the filtered data stream to an output binary file. The package also includes the utility to convert an avi video file format to and from a binary file format.
Download the files used in this example:
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Files in the zip download include:
- example_gamma_<version number>.mdl - DSP Builder design file
- gamma_corrector.vhd - Wrapper file to generate the Altera® Gamma Corrector intellectual property (IP) MegaCore function
- avi-is-avi.exe - DOS executable to convert an avi file to and from a binary file
Figure 1 shows the top-level diagram of the gamma correction design example in DSP Builder.
Figure 1. Gamma Correction Design Example
View Full Size
Table 1 lists the ports and gives a description for each.
| Table 1. Gamma Correction Port Listing |
| Port Name |
Type |
Description |
din[7:0] |
Input |
Data input bus |
din_valid |
Input |
Data valid signal that indicates the validity of the input data signals |
dout_ready |
Input |
Data output ready signal |
reset |
Input |
Reset signal |
lut_test_writeack |
Input |
Test port associated with Avalon®-MM slave port gamma_lut. Internal testing only, no need to connect to design |
av_address[8:0] |
Input |
Avalon write address bus |
av_chipselect |
Input |
Avalon chip-select signal |
av_write |
Input |
Avalon write signal |
av_writedata[7:0] |
Input |
Avalon write data bus |
din_ready |
Output |
Data input ready signal |
dout[7:0] |
Output |
Data output bus |
dout_valid |
Output |
Data valid signal that indicates the validity of the output data signals |
lut_test_writetog |
Output |
Test port associated with Avalon-MM slave port gamma_lut. Internal testing only, no need to connect to design |
av_readdata[7:0] |
Output |
Avalon read data bus |
Related Links
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
|
文档资料
> 
