Viterbi Tail-Biting Triple-Pass Decoding (P = TB)
This design example shows how to implement a communication system with Altera® DSP Builder blocks. The system consists of a convolutional encoder and Viterbi decoder. The convolutional encoder adopts the trellis termination scheme called tail-biting by initializing the starting state of each packet with the tail bits. On the decoder side, double-pass buffer and output buffer are implemented along with the Altera Viterbi intellectual property (IP) core to decode the received code words properly. In this example, packet size of 48 in the decoder is equal to three times the encoded packet size (P) of 16. You can also compare the performance of bit-error rate (BER) versus Eb/No curves with other design examples.
Download the files used in this example:
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Files in the zip download include:
- viterbi_system_triplepass.mdl — DSP Builder design file implementing the Viterbi system
- viterbi.vhd — wrapper file to generate Altera Viterbi IP core.
- init.m — MATLAB script to initialize the sampling time.
Figure 1 shows the top-level diagram of the Viterbi tail-biting system design example in DSP Builder.
Figure 1. Viterbi System Top-Level Diagram
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Figure 2 compares the performance of BER versus Eb/No curves.
Figure 2. BER vs. Eb/No performance curves
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Table 1 lists the ports and gives a description for each.
| Table 1. Viterbi System Port Listing |
| Port Name |
Type |
Description |
datain |
Input |
data input to encoder |
enain |
Input |
enable input to encoder |
rst |
Input |
reset signal |
decout |
Output |
data output from decoder |
enaout |
Output |
enable output from decoder |
Related Links
For more information on the related features used in this design example that you can use in your project, go to:
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