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主页 > 支持 > 设计范例 > DSP 打印此页 发送此页 DSP Design Examples Table 1 contains digital signal processing (DSP) design examples for use in designs for Altera® devices. To see the design example, choose the corresponding icon in the Design Entry Method column. Table 1. DSP Design Examples—Functions and Design Entry Methods Function Design Entry Method Achieving Unity Gain in Block Floating Point IFFT+FFT Pair Coefficient Reload FIR Filter Polyphase Modulation With Aliasing for Digital Up-Conversion Implementing OFDM Modulation and Demodulation Designing Digital Down Conversion Systems Using CIC and FIR Filters Using CIC Decimation Filter With Multi-channel Support CIC Interpolation Filter With Multi-Channel Data Support Deinterlacer Using Weave Mode Deinterlacer Using Bob Mode Gamma Correction YCbCr to RGB Color Space Conversion Image Frame Resizing Using Scaler Salt and Pepper Noise Removal Using 2D Median Filter Video Picture in Picture (PIP) Mixing Using Alpha Blending Mixer Chroma Resampler Up-Conversion 2D Sharpening Finite Impulse Response (FIR) Filter Viterbi Tail-Biting Double-Pass Decoding (Packet Size = Traceback Length) Viterbi Tail-Biting Double-Pass Decoding (Packet Size = 2 Traceback Length) Viterbi Tail-Biting Triple-Pass Decoding (Packet Size = Traceback Length) Complex Finite Impulse Response (FIR) Filter Bit-Error Rate (BER) Performance Measurement of Viterbi Decoder Half-Band Filter Using Distributed Arithmetic Half-Band Filter Using Distributed Arithmetic & Time Domain Multiplexing (TDM) Half-Band Filter With Reloadable Coefficients Half-Band Filter Using DSP Blocks Fast Fourier Transform With 32K Points Transform Length Complex Multiplier With Reloadable Coefficients Using Conventional Representation Complex Multiplier With Constant Coefficients Using Conventional Representation Complex Multiplier With Variable Coefficients Using Conventional Representation Complex Multiplier With Reloadable Coefficients Using Canonical Representation Complex Multiplier With Constant Coefficients Using Canonical Representation Complex Multiplier With Variable Coefficients Using Canonical Representation Viterbi Decoder With Node Synchronization Signed Multiplier Signed Multiplier With Registered I/O Signed Multiply-Accumulator Signed Multiply-Adder Unsigned Multiplier Unsigned Multiplier With Registered I/O Unsigned Multiply-Accumulator Unsigned Multiply-Adder 12 x 9 Firm Multiplier 12 x 12 Firm Multiplier Fully Variable Coefficient Soft Multiplier Hybrid Fixed Coefficient Soft Multiplier Hybrid Variable Coefficient Soft Multiplier Parallel Fixed Coefficient Soft Multiplier Parallel Variable Coefficient Soft Multiplier Semi-Parallel Fixed Coefficient Soft Multiplier Semi-Parallel Variable Coefficient Soft Multiplier Sum of Multiplication Fixed Coefficient Soft Multiplier Sum of Multiplication Variable Coefficient Soft Multiplier Discrete Cosine Transform (DCT) Basic FIR Filter Time Domain Multiplexed FIR Filter Polyphase Decimation FIR Filter Polyphase Interpolation FIR Filter Two-Dimensional FIR Filter Basic Infinite Impulse Response (IIR) Filter Butterworth IIR Filter Magnitude Function The following icons indicate the entry mode(s) used in each example: Altera hardware description language (AHDL) VHDL MAX+PLUS® II graphic editor Verilog hardware description language (HDL) Tool command language (Tcl) Quartus® II development tool Simulink model 给本页评分

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