Arithmetic Design Examples

Table 1 contains arithmetic design examples for use in designs for Altera^® devices. Select the design entry method icon to see the design example.

Table 1. Arithmetic Design Examples
Function	Design Entry Method
Adder/Subtractor	Verilog HDL VHDL
Binary Adder Tree	Verilog HDL
Ternary Adder Tree	Verilog HDL
Examples for altfp_add_sub Megafunction User Guide	Quartus® II Software
Examples for altmult_add Megafunction User Guide	Quartus II Software
Parameterized Counter (lpm_counter)	Verilog HDL
Behavorial Counter	Verilog HDL VHDL
Carry Look-Ahead Adder	VHDL
Ripple-Carry Adder	VHDL
Down Counter	VHDL
Legacy Examples
Parameterized Multiplier (lpm_mult)	AHDL MAX+PLUS® II Graphic Editor
Parameterized Counter (lpm_counter)	AHDL

Design Examples Disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.