Using altlvds With the External PLL Option in Stratix III FPGAs
The altlvds megafunction allows you to instantiate an external phase-locked loop (PLL) when using a Stratix® III FPGA. You can generate the altlvds megafunction with external PLL mode enabled by checking the Use External PLL check box in the altlvds MegaWizard® Plug-In Manager. The implementation steps related to the PLL are different for Stratix III FPGAs compared to Stratix II FPGAs. The Stratix III altpll MegaWizard Plug-In Manager does not have the Set up PLL in LVDS mode option. You can use a left/right PLL setup as a regular PLL and connect the PLL to the altlvds megafunction.
Details of the PLL settings are as follows:
- Parameter settings:
- Select left/right PLL type
- Select feedback path inside the PLL in source-synchronous compensation mode
- Clk0: High-speed serial clock connected to the rx_inclock or tx_inclock port of the altlvds megafunction
- Output frequency: Data rate
- Phase shift: -180 degrees
- Duty cycle: 50%
- Clk1: Load-enable signal connected to the rx_enable or tx_enable input port of the altlvds megafunction
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Output frequency: Data rate/deserialization factor
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Phase shift: [(deserialization factor – 2)/deserialization factor] * 360 degrees
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Duty cycle: (100/deserialization factor)%
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Clk2: Clocks the synchronization register
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If dynamic phase alignment (DPA) is used for the receiver, set the following in the wrapper file generated for the altlvds megafunction:
This setting works for all deserialization factors and data rates available with the altlvds megafunction.
Download the Quartus® II software project used in this example:
This project is a complete design that shows that the output of the altlvds transmitter megafunction implemented with the external fast PLL is the same as the altlvds transmitter megafunction with the internal PLL. Figure 1 shows the top-level design file. This design example also includes a complete vector waveform input file (.vwf) for simulation to demonstrate the functionality of the circuit.
Figure 1. Top-Level Design
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The Clk0 and Clk1 clocks are used to clock in the serializer/deserializer (SERDES) circuitry. A synchronization register must be added after the altlvds receiver megafunction for each channel. A synchronization register must also be added for each channel before the transmitter megafunction. Clk2 clocks the synchronization register in this example.
See the altlvds Megafunction User Guide (PDF) and the altpll Megafunction User Guide (PDF) for more information on the megafunctions shown here.
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