Altera Home Page
文档资料 许可
在线购买 下载

  主页   |   产品   |   支持   |   最终市场   |   技术中心   |   教育与活动   |   公司介绍   |   在线购买  
  mySupport   |   器件   |   软件   |   IP   |   设计范例   |   参考设计  

 产品
      MAX/MAX II
      Stratix/Stratix GX
      Nios II
  
 功能
      算法
      存储器
      总线及I/O
      逻辑
      接口与外设
      DSP
      通信
      PLL & Clocking
  
 设计输入方法
      Quartus II软件工程
      Tcl
      VHDL
      Verilog HDL
      C Code 范例
      DSP Builder
      TimeQuest
   片内调试
  
 仿真工具
      Mentor Graphics ModelSim
      Cadence NCsim
      Synopsys VCS
  
 旧范例
      图形编辑器
      AHDL
  

Graphic Editor: Tri-State Buses Converted to a Multiplexer

In this example, three tri-state buses feed a flipflop. Because Altera devices do not have internal device tri-state buses (i.e., tri-state buffers only exist in I/O cells), MAX+PLUS II converts the tri-state bus to a multiplexer.

Download the Graphic Editor file used in this example:

For more information on using this example in your project, go to:
tri_bus.gdf

tri_bus.gdf


Feedback

Did this information help you?

If not, please log onto mySupport to file a technical request or enhancement.


Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.

  请填写反馈意见
  注册索取最新邮件通知