This design example shows the transceiver reset controller logic which controls the reset sequence in the Triple Speed Ethernet's (TSE) transceiver as per recommended by the device handbook.
The document assumes that the user is familiar with the TSE intellectual property (IP) Core, the ALTLVDS megafunction and the transceiver architecture of the FPGA device.
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The use of this design is governed by, and subject to, the terms and conditions of theAltera Hardware Reference Design License Agreement
The transceiver reset controller (lvds_rst_ctrl) detects the reset signal to reset the phase-locked loop (PLL) of the ALTLVDS receiver using the pll_areset signal, detects the rx_locked signal to reset the ALTLVDS receiver using the rx_reset signal, and detects the rx_dpa_locked signal to reset the FIFO of the ALTLVDS receiver using the rx_fifo_reset signal according to the reset sequence in the device handbook.
Figure 1 shows the simplified block diagram of the lvds_rst_ctrl logic connect to the ALTLVDS receiver.
Figure 1. lvds_rst_ctrl connect to pma_lvds_rx (rst_lvds)
State Machine
The state machine generates control signals like pll_areset, rx_reset, and rx_fifo_reset. As shown in Figure 2, the state machine has 4 states.
Figure 2. State Machine
The following section describes the states in the state machine in more detail.
stm_idle: This is the idle state. When the reset signal is deasserted, the state transits to the next state, the stm_pll_areset.
stm_pll_areset: This is the ALTLVDS receiver's PLL reset state. In this state, the counter count_pll_areset is used to count the number of parallel clock cycles when the pll_areset output signal is asserted. After two parallel clock cycles, the pll_areset output signal is released. When the receiver is locked,the rx_locked signal is asserted, and the state transits to the next state, the stm_rx_reset.
stm_rx_reset: This is the ALTLVDS receiver's reset state. In this state, the counter count_rx_reset is used to count the number of parallel clock cycles when the rx_reset output signal is asserted. After two parallel clock cycles, the rx_reset output signal is released. When the dynamic phase alignment of the receiver is locked, the rx_dpa_locked signal is asserted, and the state transits to the next state, the stm_rx_fifo_reset.
stm_rx_fifo_reset: This is the ALTLVDS receiver’s FIFO reset state. In this state, the counter count_fifo_reset is used to count the number of parallel clock cycles when the rx_fifo_reset output signal is asserted. After two parallel clock cycles, the rx_fifo_reset output signal is released.
Points to note:
- Whenever the rx_locked signal is deasserted, the state machine returns to the stm_pll_aresetstate.
- Whenever the rx_dpa_locked signal is deasserted, the state machine returns to the stm_rx_resetstate.
For more information about instantiating TSE with external ALTLVDS, please refer to the following design example:
Instantiate TSE with External ALTGX/ALTLVDS
Related Links
- Triple Speed Ethernet (TSE) IP Core Resource Center
- Triple Speed Ethernet MegaCore Function User Guide (PDF)
- ALTLVDS Megafunction User Guide (PDF)
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