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主页 > 支持 > 设计范例 > Mentor Graphics ModelSim 打印此页 发送此页 Mentor Graphics ModelSim Simulation Design Examples Table 1 contains design examples demonstrating gate-level timing simulation of Altera® devices. Gate-level timing simulations are performed with Mentor Graphics® ModelSim® software to ensure that the post-synthesized or post-fit netlist passes the functional specifications. Table 1. Simulation Design Examples Function Design Entry Method PLL Gate-Level Timing Simulation Stratix® II GX Post-Fit Timing Simulation With ModelSim SE/PE Software Stratix II GX Post-Fit Timing Simulation With ModelSim-Altera Software Stratix II GX Post-Fit Timing Simulation With ModelSim SE/PE Software Stratix II GX Post-Fit Timing Simulation With ModelSim-Altera Software Stratix II Post-Fit Timing Simulation With ModelSim SE/PE Software Stratix II Post-Fit Timing Simulation With ModelSim-Altera Software Stratix II Post-Fit Timing Simulation With ModelSim SE/PE Software Stratix II Post-Fit Timing Simulation With ModelSim-Altera Software Simulation With NativeLink Feature in Quartus II Software The following icons indicate the entry mode(s) used in each example:  Altera hardware description language (AHDL)  VHDL  MAX+PLUS® II Graphic Editor  Verilog hardware description language (HDL)  Tool command language (Tcl)  Quartus® II development tool Related Links ModelSim-Altera Software Support Simulation and Verification Resource Center 给本页评分

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