Stratix II GX Post-Fit Timing Simulation Design Example with ModelSim SE/PE (Verilog HDL)
This Verilog HDL design example shows the simulation flow between the Mentor Graphics® ModelSim® SE/PE software and the Quartus® II design software. With this design example, you can learn how to perform gate-level timing simulations of your design implemented in Altera® Stratix® II GX devices with the Mentor Graphics ModelSim SE/PE simulator.
The design is created in Verilog HDL and consists of a top-level module (multiplier block), an altpll megafunction, an lpm_mult megafunction, an altsynram megafunction, an alt2xgxb megafunction and a testbench. The results of the multiplier are stored in the RAM and then later sent out through the GX transceiver and looped back to its own receiver.
Note: This example was developed using Quartus II 7.1 SP1 software running on a Windows XP SP2 machine and Mentor Graphics ModelSim SE 6.1g version running on the same host.
Download the alt2gxb_modelsim_SE_verilog.qar design example.
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Using This Design Example
- Unarchive the attached file to your desired location.
- Invoke the Quartus II software and load the alt2gxb_example.qpf project.
- On the Assignments menu, click EDA Tool Settings to open the Settings dialog box and then click Simulation. Verify that ModelSim is selected in the Tool name field.
- On the Quartus II software toolbar, click compile. After compilation, the Quartus II software generates a post-fit netlist named alt2gxb_example.vo (for use with the ModelSim SE/PE simulator tool) in <project_dir>/simulation/modelsim. The SDF Output File (alt2gxb_example .sdo), for annotating the delays in the gate-level timing simulation file, is also generated at the same location.
- Tor run ModelSim SE/PE software, Invoke the ModelSim SE/PE software.
- Change the directory name to <project_dir>/simulation/modelsim.
- To run the <project_dir>/simulation/modelsim/multiplier_run_msim_gate_verilog.do script, type do –alt2gxb_example_run_msim_gate_verilog.do in the ModelSim SE/PE simulator console window.
For more information on using the Mentor Graphics ModelSim simulator tool, refer to Mentor Graphics ModelSim software documentation and the Mentor Graphics ModelSim Support chapter in volume 3 of the Quartus II Development Software Handbook.
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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