Gate-Level Simulation With ModelSim-Altera Simulator
You can use this design example to learn how to perform gate-level timing simulations of your design implemented in Stratix® II devices with the Mentor Graphics® ModelSim®-Altera® simulator.
In this example you will:
- Load an existing project in the Quartus® II software
- Set up a Quartus II project to generate the right files for simulation
- Compile your design in the Quartus II software to generate a gate-level netlist
- Understand the outputs generated for gate-level timing simulation
- Run the simulation with the scripts provided and understand the results
The design is created in VHDL and consists of a top-level module (multiplier block), a phase-locked loop (PLL) megafunction, an alt_mult megafunction, an lpm_ram megafunction, and a testbench. All the device libraries required for gate-level simulation come pre-compiled with the ModelSim-Altera software
Note: This example was developed using Quartus II 6.0 SP1 software running on a Windows XP SP2 machine and Mentor Graphics ModelSim-Altera 6.1d version running on the same host.
Download the dsgn_msim_ae_vhd.zip design example.
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Using This Design Example
- Unzip the attached file to your desired location.
- Invoke the Quartus II software and load the multiplier.qpf project.
- On the Assignments menu, click EDA Tool Settings to open the Settings dialog box and then click Simulation. Verify that ModelSim-Altera is selected in the Tool name field.
Note: To use the Quartus II NativeLink feature, you must also provide the absolute path for the ModelSim-Altera software. On the Tools menu, click Options, then General, then EDA Tool Options.
- On the Quartus II software toolbar, click compile. After compilation, the Quartus II software generates a post-fit netlist named multiplier.vho (for use with the ModelSim-Altera simulator tool) in <project_dir>/simulation/modelsim. The SDF Output File (multiplier_vhd.sdo) for annotating the delays in the gate-level timing simulation file is also generated at the same location.
- Run the simulation.
- ModelSim-Altera software. Invoke the ModelSim-Altera software. Change the directory name to <project_dir>/simulation/modelsim. To run the
<project_dir>/simulation/modelsim/multiplier_run_msim_gate_vhdl_gld.do script, type
>do –multiplier_run_msim_gate_vhdl_gld.do
in the ModelSim-Altera simulator console window.
The ModelSim-Altera simulator compiles the testbench and the netlist (multiplier.vho), annotates the SDF data (in multiplier_vhd.sdo), and runs the simulation for the specified time. A waveform window within the ModelSim-Altera simulator is invoked that shows the expected and actual results of the multiplier. The expected and actual results are also checked in the testbench, and messages that show whether or not the results match are displayed in the simulator’s console window. The data output of the multiplier module changes with a delay after the clock edge because the SDF data is annotated in the gate-level timing simulation.
For more information on using the Mentor Graphics ModelSim simulator tool, refer to Mentor Graphics ModelSim software documentation and the Mentor Graphics ModelSim Support chapter in volume 3 of the Quartus II Development Software Handbook.
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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