To manually run simulation without using the Quartus® II NativeLink feature, perform the following steps. You can use these steps for the ModelSim®-Altera® and ModelSim SE/PE software.
Step 1: Invoke Software and Change Directory
- Invoke the Modelsim-Altera software.
- Go to File menu, select the change directory name to <project_dir>/simulation/modelsim.
ModelSim-Altera Software
Step 2: Create a New Library
- Go to File menu, select New, and click the library.
- Type work in the Library Name column, then click OK.
Step 3. Compile the Library and Design File
- Go to Compile, and then select Compile.
- Select work library then look in the <project directory> for the design file.
Below is the library and design file needed to compile for this example. - Click Done.
Note: For Modelsim-Altera software, there is a pre-compiled simulation library.
ModelSim SE/PE Software
Step 2: Create a New Library
- Go to File menu, select New, and click the library.
- Type lpm_ver in the Library Name column, then click OK.
Note: Repeat Step 2: Create a New Library for more libraries. This step will create the library folder and map the library.
Step 3: Compile the Library and Design File
- Go to Compile, and then select Compile.
- Select the specific library folder that you created in Step 2: Create a New Library and look in the <Quartus II installation folder> for the sim_lib to compile
(e.g., c:\altera\90sp2\quartus\eda\sim_lib). - After you select the folder and library, click Compile.
- Click Done.
For more information on using the Mentor Graphics ModelSim simulator tool, refer to Mentor Graphics ModelSim software documentation and the Mentor Graphics ModelSim Support (PDF) chapter in volume 3 of the Quartus II Development Software Handbook.
Table 1 provides information allowing you to choose which library is needed to compile for VHDL and Verilog.
| Table 1. VHDL and Verilog Libraries | |
VHDL |
Verilog |
|---|---|
Folder name: Lpm File to compile: <220model.vhd, 220pack.vhd> |
Folder name: lpm_ver File to compile: 220model.v |
Folder name: Sgate File to compile: <sgate.vhd, sgate_pack.vhd> |
Folder name: sgate_ver File to compile: sgate.v |
Folder name: stratixiigx_hssi File to compile: <stratixiigx_hssi_atoms.vhd,stratixiigx_hssi_component.vhd> |
Folder name: stratixiigx_hssi_ver File to compile: stratixiigx_hssi_atoms.v |
Folder name: stratixiigx File to compile: |
Folder name: stratixiigx_ver File: stratixiigx_atoms.v |
Folder name: work File to compile: design files that have the extension .vo and .vht |
Folder name: work File to compile: design files that have the extension .vo and .vt |
Step 4: Start Simulation
- Go to Simulate, click Start Simulation.
- At the Design tab, search for work, then expand the work and select your testbench file.
- At the Libraries tab, click Add.
- Select library lpm, then click OK.
- Repeat step 3 for more libraries.
- Click OK.
Note: For this design, you need to include the following libraries, sgate, lpm, stratixiigx_hssi, stratixiigx, work, and gate_work.
Step 5: Add Wave and Run Simulation
- Go to the View menu, select Wave.
- Select the entire signal at the object panel or drag the signal that you wish to look at to the wave panel.
- At the Transcript window, type runs 1000ns.
