Gate-Level Simulation With Cadence NC-Sim Simulator
You can use this design example to learn how to perform gate-level timing simulations of your design implemented in Stratix® II devices with the Cadence NC-Sim simulator.
In this simulation design example, the gate-level netlist (multiplier.vo) and SDF data (multiplier_v.sdo) are generated from the Quartus® II software after the compilation step. A separate testbench instantiates the design under test (DUT) and applies the stimulus. The testbench module (multiplier_vlg_vec_tst) resides in the multiplier.vt file.Two scripts, RunMe and script.bat, are provided to parse and elaborate the input files and launch the GUI (Simvision) of the Cadence Incisive platform. The device libraries required in this simulation example are also provided with the design files.
Note: This example was developed using Quartus II 6.0 SP1 software running on a Windows XP SP2 machine and Cadence NC-Sim version 5.4-s020 running on the same host. You can also use the UNIX or Linux version of the Cadence NC-Sim software to run this simulation design example.
Download the dsgn_ncsim_ver.zip design example.
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Using This Design Example
Follow these steps to use the design example.
- Unzip the attached file to the desired location.
- For Windows XP, change the directory to <location_of_files>. Run the script.bat script by typing
><location_of_files>/script.bat at the command prompt.
- For UNIX/Linux, change the directory to <location_of_files >. Run the RunMe script by typing
%<location_of_files>/source RunMe at the command prompt.
For both platforms, the Cadence simulator compiles the libraries provided, the testbench, and the netlist (multiplier.vo); annotates the SDF data; and invokes the Simvision GUI. You can pull in the signals of interest to a waveform window and start the simulation. For more information on using Cadence simulation tools, refer to Cadence NC-Sim software documentation and the Cadence NC-Sim Support (PDF) chapter in volume 3 of the Quartus II Development Software Handbook.
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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