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主页 > 支持 > 设计范例 > Cadence NCsim 打印此页 发送此页 Cadence NC-Sim Simulation Design Example To get you started quickly on performing simulations with Cadence NC-Sim simulator, Altera offers a design example for use in designs for Altera® devices. The design example in Table 1 demonstrates gate-level timing simulation of Altera devices. The gate-level netlist and the Standard Delay Format (SDF) data for the design are produced from Quartus® II software after design compilation. Gate-level timing simulations of the netlist are performed with Cadence NC-Sim software to ensure that the synthesized netlist passes the functional specifications after the place and route (compilation) of your design. Table 1.Simulation Design Example Simulation Type Design Entry Method Stratix® II Post-Fit Timing Simulation With Cadence NC-Sim Simulator The following icons indicate the entry mode(s) used in the example:  Altera hardware description language (AHDL)   VHDL  MAX+PLUS® II Graphic Editor  Verilog hardware description language (HDL)  Tool command language (Tcl)  Quartus II development tool Related Link Simulation and Verification Resource Center 给本页评分

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