Nios II Ethernet Acceleration Design Example
This design example demonstrates how to achieve high levels of networking performance using the Nios© II processor, the NicheStack Networking Stack Nios II Edition, and the Altera® Triple Speed Ethernet MAC (TSE MAC).
This example also uses the TSE-SGDMA design example for the Nios II Development Board, Stratix® II Edition (RoHS compliant). The TSE-SGDMA design example for the TSE MAC uses the Scatter Gather DMA (SGDMA) peripherals to move data and operate at a clock frequency of 83.3 MHz. However, to increase overall networking performance, several optimizations have been applied to the system design.
This design example incorporates the addition of an MRAM memory to increase the data throughput of the SGDMA peripherals when sending and receiving Ethernet data grams. Additionally, this example incorporates a hardware-accelerated network checksum to speed up processing of Ethernet data grams. This hardware checksum was created using the Altera C-to-Hardware Acceleration Compiler (C2H Compiler).
A simple network benchmark program is also included as a part of this example to measure the effective throughput of TCP and UDP data transfers. Additionally, you can use this benchmark program to measure how various hardware and software optimizations impact the total networking performance of the system.
Required Hardware and Software
- Quartus® II, version 7.1 (or later)
- Nios II EDS, version 7.1 (or later)
- Nios II Development Kit, Stratix II Edition (RoHS compliant)
Hardware Design Specifications
The hardware design used in this example targets the Nios II Development Board, Stratix II Edition. Key peripherals in this design include the following:
- Nios II processor core (Nios II/f core with instruction and data cache)
- Altera TSE MAC 10/100/1000 Mbits
- SGDMA for sending and receiving data
- FIFO bridge
- DDR SDRAM memory
- SSRAM memory
- MRAM memory (for packet storage)
- C2H accelerated network checksum
Software Design Specifications
C source files are included for the benchmark program and compile for the Nios II processor or Windows workstation. The benchmark program also uses the Nios II Hardware Abstraction Layer (HAL) and NicheStack Networking Stack, Nios II Edition for its operation.
Download This Design Example
Download the Nios II Accelerated TSE MAC design (.zip file).
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
The .zip file contains all the necessary software files to reproduce the example for the Nios II Development Kit, Stratix II Edition, as well as a readme.doc file. The readme.doc file contains instructions for rebuilding the example.
Download the Application Note
This example was created using the recommendations found in the Altera application note AN 440: Accelerating Nios II Networking Applications. This application note provides a detailed analysis of how to increase the performance of your Nios II networking application and includes benchmark results for various systems.
Download AN 440: Accelerating Nios II Networking Applications (PDF).
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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