Fast Nios II Hardware Design Example
This design example highlights the Dhrystone millions of instructions per second (MIPS) performance of the Nios® II processor. It includes the Fast hardware design and the Dhrystone benchmark software application. The system achieves over 200 Dhrystone MIPS in the Nios II /f core running on a Stratix® II FPGA. You can use this design with the Nios II development kit, Stratix II Edition, and the Cyclone® III FPGA development kit.
Using This Design Example
Download this example. Refer to the readme.txt file for more details.
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Design Specifications
- Board support: Nios II development kit, Stratix II Edition, and Cyclone III FPGA development kit
- Nios II core: Nios II /f, 4 Kbytes i-cache, 2 Kbytes d-cache
- JTAG debug module: Yes
- On-chip RAM: 64 Kbytes
- JTAG UART: 1
- Timer: 1
Related Links
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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