Nios II Multiprocessor Design Example
This design example demonstrates the use of multiple Nios® II CPUs in an Altera® FPGA. The example is primarily aimed at demonstrating a properly constructed hardware system, although it also contains software to exercise the inter-processor communication capabilities of the system.
The hardware portion of the example is created in SOPC Builder and contains three Nios II CPUs. The three CPUs all share system memory, including SDRAM, SSRAM, CFI flash, and on-chip RAM. Each CPU is configured to run application code from its own section of SDRAM, but data in the on-chip RAM can be shared between CPUs using the Mutex component. The Mutex component is a hardware peripheral that helps the CPUs coordinate access to shared peripherals or memory without the danger of corrupting each other's written data.
The software portion of the example is a single C file. The C file demonstrates inter-processor communication using the Mutex component and on-chip RAM. The CPUs take turns writing messages to a shared on-chip RAM message buffer. The CPUs use the Mutex component to guarantee exclusive ownership of the RAM before writing their message. One of the three CPUs also checks the message buffer periodically. If the buffer contains a message, the CPU prints the message to the jtag_uart peripheral then empties the buffer, freeing it for other CPUs to write new messages.
Hardware Design Specifications
- Board support
- Nios Development Board, Cyclone® II edition
- Nios Development Board, Stratix® II restriction of hazardous substances (RoHS) edition
- Nios II/s CPU core, debug-enabled, 4 Kbytes I-cache: 3
- System timer: 3
- High resolution timer peripheral: 1
- On-chip RAM: 1 Kbyte
- Off-chip synchronous SRAM: 1 Mbyte
- Common flash interface (CFI) flash memory interface: 8 Mbytes
- SDRAM controller: 32 Mbytes
- JTAG UART: 1
- Button PIO peripheral: 1
- LED PIO peripheral: 1
- Mutex peripheral: 1
- System ID peripheral: 1
- Phase-locked loop (PLL): 1
This design example is based on the system constructed in the Nios II Multiprocessor Tutorial (PDF). For detailed information about implementing Nios II multiprocessor systems, please refer to the tutorial.
Block Diagram
Figure 1. Nios II Multiprocessor System Block Diagram
Using This Design Example
Download the .zip file for whichever Nios II development board you have.
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
The .zip file contains all the necessary hardware and software files to reproduce the example, as well as a readme.txt file. The readme.txt file contains instructions for re-building and running the design.
Related Links
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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