Off-Chip Memory PLL Tuning Design Example
The Nios® II Off-Chip Memory PLL Tuning design example determines the valid signal window for accessing the memory device. Improper clocking of memory devices can cause issues such as not being able to run code or perform back-to-back transactions to the memory.
This design example tests the SDRAM memory device on the target board and calculates the recommended shift for the SDRAM clock (relative to the SDRAM controller clock) by scanning through the SDRAM clock period. It uses a Nios II processor and a custom SOPC Builder component that accesses the reconfiguration interface of the PLL. You can use the results of the tests, which are printed to a terminal window, to configure the PLL output driving the SDRAM clock.
The hardware portion of the example is created in SOPC Builder and contains the necessary peripherals to read the PLL parameters from the altpll_reconfig megafunction, shift the SDRAM clock output of the PLL, test the SDRAM memory, and calculate the boundaries and center of the SDRAM valid signal window. Direct memory access (DMA) is used for testing the SDRAM memory because it provides a more rigorous test, including back-to-back transactions. An SOPC Builder component is provided that has an Avalon® wrapper around the altpll_reconfig megafunction. This component accesses the reconfiguration interface of the PLL. The hardware design also contains a JTAG UART that reports the valid signal window.
The software portion of the example is a Nios II integrated development environment (IDE) project written in C. The software program reads parameters from the altpll_reconfig megafunction to determine the PLL VCO frequency, the SDRAM clock shift amount, and the number of shifts necessary to shift through the SDRAM clock period. Then, a loop is executed that iteratively tests the SDRAM memory and shifts the SDRAM clock. The boundaries and the middle of the valid SDRAM signal window are calculated and reported to you via the JTAG UART.
Hardware Design Specifications
- Board support: Nios Development Board, Stratix® II edition (non-RoHS)
- Instructions are provided for porting the design to your board
- Device support: Stratix II devices only because of PLL reconfiguration features
- Not supported on Stratix II EP2S15 because of memory requirements
- Nios II core: Nios II/e, debug-enabled
- On-chip RAM: 64 Kbytes
- SDRAM controller: 32 Mbytes
- DMA controller: 1
- PLL: 1
- PLL reconfiguration controller: 1
- JTAG UART: 1
- Timer: 1
- System ID peripheral: 1
Block Diagram
Figure 1 shows the block diagram for the Nios II off-chip memory PLL tuning system.
Figure 1. Nios II Off-Chip Memory PLL Tuning System Block Diagram
Using This Design Example
Download the Nios II Off-Chip Memory PLL Tuning Design Example (ZIP file).
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
The ZIP file contains all the necessary hardware and software files to reproduce the example, as well as a readme.txt file. The readme.txt file contains instructions for running the example on the Nios Development Board, Stratix II edition (non-RoHS). It also contains instructions for porting the design to your board.
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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