Synopsys设计约束(SDC)格式提供简单而又直接的方法来约束最简单和最复杂的设计。以下是最简单的SDC文件内容，约束设计中的所有时钟(端口和引脚)、输入I/O通道、输出I/O通道。
# Global fMAX of 100 MHz
# All detected clocks will be constrained with a 100 MHz requirement
derive_clocks -period "100MHz"
# Automatically apply a generate clock on the output of phase-locked loops (PLLs)
# This command can be safely left in the SDC even if no PLLs exist in the design
derive_pll_clocks
# Constrain the input I/O path
set_max_delay -from [all_inputs] -to [all_registers] 1
set_min_delay -from [all_inputs] -to [all_registers] 2
# Constrain the output I/O path
set_max_delay -from [all_registers] -to [all_outputs] 3
