Verilog HDL: Atlantic 2-to-1 Width Converter
The AtlanticTM interface is a simple, standardized, on-chip data path interface that enables the rapid integration of IP MegaCore® functions. This register transfer level (RTL) design example shows how to connect together two MegaCore functions that have Atlantic interfaces of different widths. Figure 1 shows a typical application.
Figure 1 shows the connections for a sink-master, 2-to-1 converter block; the clock and reset signals are not shown. For every cycle of data from the source, the 2-to-1 converter writes two cycles of data to the sink. While it is writing the second cycle, the converter stops the source from providing new data. Because of this ability and requirement to turn off the source, a 2-to-1 converter can only function with a sink-master interface. To perform a 2-to-1 conversion for a source-master interface, a buffer is required to absorb data from the source, while the converter writes two cycles to the sink with the converter controlling the read side of the buffer, thereby turning the interface between the buffer and the sink into a sink-master interface.
Figure 1. Atlantic 2 to 1 Interface Width Converter Top-Level Block Diagram
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Table 1 lists and describes the signals.
| Table 1. Atlantic 2-to-1 Width Converter Design Example Signals |
| Signal |
Type |
Description |
clk |
Input |
Reference clock |
reset_n |
Input |
Active-low, synchronous reset |
ai_rddav |
Input |
Read data available |
Atlantic Input Interface
(Sink Master) |
ai_rdena |
Output |
Read enable, connects to ena |
ai_wrena |
Input |
Write enable, connects to val |
ai_sop |
Input |
Start of packet |
ai_eop |
Input |
End of packet |
ai_err |
Input |
Errored packet |
ai_dat[127:0] |
Input |
Data |
ai_mty[3:0] |
Input |
Empty bytes |
ai_adr[7:0] |
Input |
Address |
ao_rddav |
Output |
Read data available |
Atlantic Output Interface
(Source Slave) |
ao_rdena |
Input |
Read enable, connects to ena |
ao_wrena |
Output |
Write enable, connects to val |
ao_sop |
Output |
Start of packet |
ao_eop |
Output |
End of packet |
ao_err |
Output |
Errored packet |
ao_dat[63:0] |
Output |
Data |
ao_mty[2:0] |
Output |
Empty bytes |
ao_adr[7:0] |
Output |
Address |
Implementation
The following sections briefly discuss the implementation of the 2-to-1 Atlantic interface width converter design example.
Data Available (dav) Signal
The rddav signal is wired directly through the converter block from the source to the sink and is not used by the converter logic.
Read Enable (rdena) Signal
The sink’s rdena signal is used internally as an enable signal; therefore the output of the converter changes only when the sink allows it. This same rdena signal is used to drive the read enable to the data source; the converter uses this signal to make the data source provide new data only once every two clock cycles. The source’s ai_rdena signal is asserted only when the sink’s read enable signal is asserted, and then only when valid data is not provided.
Conversion Algorithm
Figure 2 shows the conversion algorithm flowchart. As you can see, the converter block does nothing if the read enable from the sink is not asserted; the outputs remain fixed. If the read enable is asserted, and the tophalfsent flag is not asserted (meaning that a two-cycle transfer to the sink has yet to start), then the converter block waits for the source’s ai_wren signal to be asserted, telling it that there is new data.
When new data is available, the converter loads the top half of the input data into the output data register, and sets the sop, addr, and err flags according to the inputs. As long as the input is not an EOP and the bus is not mostly empty, the converter stops for this cycle, and continues loading the bottom half of the bus on the next cycle. If the input is an EOP and the bus is mostly empty, then the converter asserts the sink’s EOP, thus setting the mty value for the smaller bus width. This completes the transfer to the sink, but the source’s ai_rdena signal has yet to be asserted, so on the next clock cycle, there will not yet be new data available; ai_wren will still be set with the old data. To get around this, the tophalfsent flag is left asserted, causing the next clock cycle to be wasted.
On the second cycle, assuming ai_rdena is asserted, the tophalfsent flag is set, meaning that the top half of the data has already been sent out at the inputs, and only the bottom half remains to be sent. The output registers are updated with the bottom half of the input data bus, and the tophalfsent flag is cleared so that the converter is ready for a new transfer. If the input is not a mostly-empty EOP transfer, then ao_wren is asserted, driving the data to the sink. If the input is a mostly-empty EOP transfer, this cycle is wasted.
Figure 2. Atlantic 2-to-1 Bus Width Converter Decision-Making Flowchart
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