Verilog HDL: Atlantic Loopback
This design example presents a small block that can be used to loop the output from an AtlanticTM source-slave back to the input of an Atlantic sink-slave. Figure 1 shows a typical application for a loopback of this type. This design example has a 128-bit Atlantic interface, and assumes that the near-side receive and transmit interfaces are both slave interfaces, such as the read- and write-side of a buffer. When the loopback input is not asserted, the far-side transmitter and receiver blocks are interface masters that control the near-side blocks. When the loopback input is asserted, the loopback block itself acts as the interface master, reading data from the near-side receiver, and pushing that data into the near-side transmitter.
Figure 1. Atlantic Loopback Top-Level Diagram
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Table 1 lists and describes the signals.
| Table 1. Atlantic Loopback Design Example Signals |
| Signal |
Type |
Description |
clk |
Input |
Reference clock |
loopback |
Input |
Loopback control: '0' passes ain to aout, and bin to bout; '1' enables loopback functionality. |
ain_dav |
Input |
Atlantic sink-master "A input" interface |
ain_val |
Input |
ain_sop |
Input |
ain_eop |
Input |
ain_err |
Input |
ain_dat[127..0] |
Input |
ain_mty[3:0] |
Input |
ain_adr[7:0] |
Input |
ain_ena |
Output |
aout_dav |
Output |
Atlantic sink-master "A output" interface |
aout_val |
Output |
aout_sop |
Output |
aout_eop |
Output |
aout_err |
Output |
aout_dat[127..0] |
Output |
aout_mty[3:0] |
Output |
aout_adr[7:0] |
Output |
aout_ena |
Input |
bin_dav |
Output |
Atlantic source-master "B input" interface |
bin_sop |
Input |
bin_eop |
Input |
bin_err |
Input |
bin_dat[127..0] |
Input |
bin_mty[3:0] |
Input |
bin_adr[7:0] |
Input |
bin_ena |
Output |
bout_dav |
Input |
Atlantic source-master "B output" interface |
bout_sop |
Output |
bout_eop |
Output |
bout_err |
Output |
bout_dat[127..0] |
Output |
bout_mty[3:0] |
Output |
bout_adr[7:0] |
Output |
bout_ena |
Output |
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