This example describes a 16-bit binary adder tree in Verilog HDL. For devices that contain 4-input lookup tables in logic element (LEs), structuring adder trees as binary adder trees can give significant performance improvement.
Figure 1. Binary Adder Tree Top-Level Diagram
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Table 1 lists the ports and gives a description for each.
| Table 1. Binary Adder Tree Port Listing | ||
| Port Name | Type | Description |
A[15:0], B[15:0], C[15:0], D[15:0], E[15:0] |
Input | 16-bit inputs to adder tree |
clk |
Input | Clock |
out[15:0] |
Output | 16-bit output of adder tree |
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