Verilog HDL: Counter with Asynchronous Reset
This example describes an 8-bit counter with asynchronous reset and count enable inputs in Verilog HDL. Synthesis tools detect counter designs in HDL code and infer lpm_counter megafunction.
Figure 1. Counter with Asynchronous Reset Top-Level Diagram
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The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Table 1 lists the ports and gives a description for each.
| Table 1. Counter with Asynchronous Reset Port Listing |
| Port Name |
Type |
Description |
clk |
Input |
Clock |
reset |
Input |
Asynchronous reset |
ena |
Input |
Count enable |
result[7:0] |
Output |
8-bit counter output |
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