In this example, you’ll learn how to create a differential pin pair for Altera® devices in Quartus® II software. This example was developed with Quartus II software version 7.2 using a Stratix® III device and is written in Verilog HDL. You must have access to Quartus II software version 7.2 or later to run this example.
Using the Pin Planner
To create a differential pin pair using the pin planner, define a single-ended pin as a top-level pin in your design. Then, create the differential pin pair in the pin planner. To do this with the attached example file, follow these steps:
- From the Project menu, click Restore Archived Project to unarchive the project.
- From the Processing menu, select Analyze and Synthesize to synthesize.
- Open the pin planner and assign the LVDS differential standard to the my_input node.
- Assign a valid pin location, for example, PIN_AG19 , to the single-ended top-level pin (my_input) in the all pins list of the pin planner. Quartus II software automatically creates the negative pin for that top-level pin. In this example, when you assign a valid pin location to the top-level pin my_input, Quartus II software creates a my_input(n) signal automatically. You can find the newly created signal in the all pins list of the pin planner. The I/O standard and location assignments made in the pin planner are saved in the .qsf file
- Compile the design by clicking Compile on the Quartus II toolbar. After compilation, review the output reports in the resource section to verify that the differential pin was implemented.
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
To learn more about the pin planner, refer to the I/O Management (PDF) chapter in the Quartus II Development Software Handbook.
Using the Assignment Editor
To create a differential pin pair using the assignment editor, define a single-ended pin as a top-level pin in your design. Then, create the differential pin pair in the assignment editor. To create a differential pin pair with the attached example file, follow these steps:
- From the Project menu, click Restore Archived Project to unarchive the project.
-
From the Processing menu, select Analyze and Synthesize to synthesize.
- Open the assignment editor and use the node finder utility to select the top-level pin my_input. Use the I/O standard assignment and enter the differential standard LVDS in the value field.
-
Using the location assignment, assign a valid pin location, for example, PIN_AG19, to the top-level pin my_input. The assignments are written to the .qsf file.
- Compile your design. During compilation, Quartus II software automatically creates the negative pair my_input(n) of the top-level pin my_input and assigns it to the negative pin location of the differential pin pair location.
- After compilation, observe the output reports in the resource section to verify that the differential pin was implemented.
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Using the Synthesis Attribute
You can also create differential pins in your HDL code. Define a single-ended pin as a top-level pin in your code and use a synthesis attribute in the HDL code to define the differential standard. Follow these steps to learn how to create a differential pair using the synthesis attribute.
- From the Project menu, click Restore Archived Project to unarchive the project.
- Open the Verilog file diff_io.v and observe how "my_input" input is defined using the Altera attribute for the differential standard.
- Compile your design by clicking Compile on the Quartus II toolbar. During the compilation, Quartus II software creates the negative pin my_input(n)of the differential pin pair. If you use a chip_pin attribute to assign a pin location for the positive pin in HDL code, Quartus II software assigns the negative pin of the differential pair appropriately.
- After compilation, observe the output reports in the resource section to verify that the differential pin has been implemented.
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
To learn more about Altera synthesis attributes, refer to the Quartus II Integrated Synthesis (PDF) chapter and/or the I/O Management (PDF) chapter of the Quartus II Development Software Handbook.
Using Differential Low-Level Primitives
For advanced devices such as Stratix® III and Cyclone® III FPGAs, you can define a differential pin pair in the HDL code of your design. The following Verilog HDL code shows an example where ALT_INBUF_DIFF is instantiated to define the positive and negative pins of the differential pin pair.
ALT_INBUF_DIFF diff_in (
.i (my_input_p),
.ibar (my_input_n),
.o (tmp)
);
defparam diff_in.io_standard = "LVDS";
defparam diff_in.location = "IOBANK_3C";
Where my_input_p and my_input_n are positive and negative input pins, respectively, of the differential pair and tmp is an internal wire. Parameters are used to assign the differential LVDS standard and I/O bank location for the differential pair. Follow these steps to learn how to create a differential pin pair using low-level primitives.
- From the Project menu, click Restore Archived Project to unarchive the project.
- Open the verilog file diff_io.v and observe how the my_input_p and my_input_n connections are made using the low-level primitive ALT_INBUF_DIFF.
- Compile your design by clicking Compile on the Quartus II toolbar. After the compilation, observe the output reports in the resource section reports to verify that the differential pin has been implemented.
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
To learn more about low-level differential primitives, refer to Quartus II software help or the Designing with Low-Level Primitives User Guide (PDF).
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
