This example describes a dual clock synchronous 64-bit x 8-bit RAM design with different read and write addresses in Verilog HDL. Synthesis tools detect dual port RAM designs in HDL code and infer altsyncram or altdpram megafunctions depending on the target device architecture.
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Table 1 lists the ports and gives a description for each.
| Table 1. Dual Clock Synchronous RAM Port Listing | ||
| Port Name | Type | Description |
data[7:0] |
Input | 8-bit data input to RAM |
read_addr[5:0] |
Input | 6-bit read address input to RAM |
write_addr[5:0] |
Input | 6-bit write address input to RAM |
we |
Input | Write enable |
read_clock |
Input | Read clock |
write_clock |
Input | Write clock |
q[7:0] |
Output | 8-bit data output of RAM |
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