Verilog: FFT With 32K-Point Transform Length
This example describes a 32K-point fast Fourier transform (FFT) using the Altera® FFT IP MegaCore® . The FFT is a discrete Fourier transform (DFT) algorithm which reduces the number of computation needed from O(N2) to O(NlogN) by decomposition. The DFT of a sequence x(n) is given by the following equation:
 where k = 0, 1, … N-1 and N is the transform length.
In this design example, the transform length, N, is 32768. Using the decimation in time (DIT) method, the design breaks down the input sequence into odd and even samples which feeds into the two individual 16K-point FFT blocks implemented in parallel using the FFT IP MegaCore. The results from the FFT IP MegaCore are recombined and reordered to obtain the final FFT output. This is shown in Figure 1. Similar to the FFT IP MegaCore, the design example uses Atlantic compliant input and output interfaces.
Download the files used in this example:
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Files in the zip download include:
- fft_32K.v—Top level design file implementing the 32K-point FFT
- parse_fft_input.v—Reorders the input sample into even and odd samples to feed into the two smaller 16K-point FFT blocks
- fft_small.v—Wrapper file generated by the FFT IP MegaCore. The core is configured to implement transform length of 16K, and it uses the streaming I/O data flow structure.
- combine_fft.v—Recombines the output of the individual 16K-point FFT blocks using the appropriate twiddle factors
- fft_32K_streaming_tb.v—Testbench for RTL simulation
- fft_32K_streaming_vo_msim.tcl—TCL script to automate the RTL simulation process in ModelSim
- fft_32K_tb.m—MATLAB model to verify the RTL simulation results
Figure 1 shows the top-level diagram of the 32K-point FFT design example.
Figure 1. Top-Level Diagram of 32K-Point FFT Design
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Table 1 lists the ports and gives a description for each.
| Table 1. 32K-Point FFT Port Listing |
| Port Name |
Type |
Description |
data_real_in[15:0], data_imag_in[15:0] |
Input |
16-bit complex data inputs |
clk |
Input |
FFT system clock |
reset |
Input |
Active high reset |
master_sink_dav |
Input |
Master sink data available signal: Asserted by the FFT slave data source to indicate the availability of data sample for input to the FFT function |
master_sink_ena |
Output |
Master sink write enable signal: Asserted by the FFT function to indicate that data can be written into the function |
master_sink_sop |
Input |
Input start of packet: Indicates to the FFT function the start of an input data block. Should be asserted for one clock cycle synchronous with the first input data sample |
fft_real_out[15:0], fft_imag_out[15:0] |
Output |
16-bit complex data outputs |
exponent_out[5:0] |
Output |
Signed block exponent: Accounts for scaling of internal signal values during FFT computation |
master_source_dav |
Input |
Asserted by the slave sink on the output of the FFT function to indicate that it can accept one block of output samples |
master_source_ena |
Output |
Master source enable: Asserted by the FFT function when data is available to be output by the FFT |
master_source_sop |
Output |
Output start of packet: Asserted on first output sample of each block |
master_source_eop |
Output |
Output end of packet: Asserted on last output sample of each block |
Related Links
For more information on related features used in this design example in your project, go to:
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