Verilog: Coefficients Reload Design Example for FIR Compiler
This design example demonstrates how to reload coefficients from a file when using the Altera® finite impulse response (FIR) Compiler IP MegaCore®function. FIR Compiler provides the flexibility to change the coefficients at run time. While the FIR Compiler is processing the data with one set of coefficients, you can reload another set without halting core processing.
To optimize silicon efficiency, coefficients are not stored in their natural order. This example explains the steps reordering the coefficients using the precompiled executable coef_seq.exe. The filter uses four sets of coefficients: low pass, high pass, band pass, and band reject filters. The first two are parameterized in the IP Toolbench; the latter two must be reloaded at run-time and require reordering in advance. The provided testbench shows you how to set up controls to reload the coefficients to meet the timing requirements.
Download the files used in this example:
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Files in the zip download include:
- fir72.v - FIR compiler wrapper file
- coef_reload_tb.v - Testbench file
- coef_reload_msim.tcl - Tcl script for running a functional simulation using the ModelSim® tool
- coef_seq.exe - Windows executable that reorders the coefficients
Figure 1. FIR Compiler Port Listing
Table 1 lists the FIR compiler ports and gives a description for each.
| Table 1. FIR Compiler Port Listing |
| Port Name |
Type |
Description |
clk |
Input |
Clock signal |
reset_n |
Input |
Synchronous active low reset signal |
sink_data[15:0] |
Input |
Sample input data |
coef_set |
Input |
Select which coefficient set used for the calculation |
sink_valid |
Input |
Asserted when input data is valid |
source_ready |
Input |
Asserted by the downstream module if it is able to accept data |
sink_error[1:0] |
Input |
Error signal indicating Avalon®-ST protocol violations on the sink side |
coef_set_in |
Input |
Selects which coefficient set to be reloaded |
coef_we |
Input |
Active high write enable signal |
coef_in[17:0] |
Input |
Input coefficient value when reloading coefficient |
source_data[37:0] |
Output |
Filter output |
sink_ready |
Output |
Asserted by the FIR filter when it is able to accept data |
source_valid |
Output |
Asserted by the FIR filter when there is valid data to output |
source_error[1:0] |
Output |
Error signal indicating Avalon-ST protocol violations on the source side |
Table 2 shows the FIR compiler parameters.
| Table 2. FIR Compiler Parameters |
| FIR Parameters |
Values |
| Filter Rate |
Single |
| # of Input Channels |
1 |
| Input Bitwidth |
16 |
| Output Bitwidth |
38 (Full Resolution) |
| Coefficient Bitwidth |
16
|
| # of Coefficient Set |
2
|
| # of Coefficient in Each Set |
40
|
| Device Family |
Stratix® II |
| Structure |
DA: Fully Parallel Filter |
| Pipeline Level |
1 |
| Data Storage |
Logic Cells |
| Coefficient Storage |
M512 |
| Coefficient Reload Box |
checked |
| Use Single Clock Box |
checked |
Related Links
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
|
文档资料
> 
