Verilog HDL: High-Speed Differential I/O Capability
The Quartus® II software high-speed differential I/O design example consists of three megafunctions:
- LVDS receiver (
altlvds_rx)
- Multiplier (
lpm_mult)
- LVDS transmitter (
altlvds_tx).
The LVDS receiver, multiplier, and LVDS transmitter modules are created using the Quartus II software MegaWizard® Plug-In. They are connected as shown in Figure 1, which illustrates the performance of:
- Converting 840 megabits per second (Mbps) serial data into 8-bit parallel data using
altlvds_rx
- Multiplication of the two 8-bit parallel data using
lpm_mult
- Converting the parallel data coming out of the multiplier into serial data using
altlvds_tx
Figure 1. Diff_io_top Top-Level Block Diagram
The multiplier will be implemented in a dedicated digital signal processing (DSP) block within the Altera® Stratix™ device. The motive behind this example is to show the data conversion. A test bench is created in Verilog and simulated using the ModelSim® tool.
Download the files used in this example:
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Table 1 lists the files included in the download. Table 2 lists the ports and gives a description for each.
| Table 1. Files included in diff_io_top.zip |
| Directory |
File |
Description |
| src |
diff_io_top.v |
Top-level design file that instantiates the receiver, multiplier, and transmitter |
| lvds_rx.v |
LVDS receiver generated by the MegaWizard Plug-In |
| mult.v |
8-bit multiplier generated by the MegaWizard Plug-In |
| lvds_tx.v |
LVDS transmitter generated by the MegaWizard Plug-In |
| sim |
testbench.y |
Instantiates the top-level module and consists of the test vectors |
| diff_io_top.vo |
Quartus II software-generated Verilog netlist to be used with the ModelSim tool |
| diff_io_top.sdo |
Quartus II software-generated SDF timing file |
| comp_altera_lib.do |
Script to compile the Stratix library |
| comp_gate.do |
Script to compile the testbench and the gate-level netlist |
| gate_sim.do |
Script to run the design in the ModelSim tool |
| Stratix library |
ModelSim compiled models |
| Table 2. High-Speed Differential I/O Design Example Port Listing |
| Port Name |
Type |
Description |
| rx_in[0] |
Input |
1-bit unsigned serial input binary data |
| rx_in[1] |
Input |
1-bit unsigned serial input binary data |
| rx_inclock |
Input |
Input clock with frequency of 105 MHz |
| tx_out[0] |
Output |
1-bit unsigned serial output binary data |
| tx_out[1] |
Output |
1-bit unsigned serial output binary data |
| tx_outclock |
Output |
Output clock from phase-locked loop (PLL) with frequency of 105 MHz |
Simulating the Design
- Invoke the ModelSim 5.6c tool.
- Change directory to the location where the simulation files are located.
- Source the script gate_sim.do by using the command:
VSIM > do gate_sim.do
Result of multiplication appears after 180 ns.
Related Links
For more information on using this example in your project, go to:
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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