Verilog HDL: Signed Multiply-Adder
This example describes a 16-bit signed Multiply-Adder design in Verilog HDL. Synthesis tools detect Multiply-Adder designs in HDL code and infer altmult_add megafunction.
Figure 1. Signed Multiply-Adder Top-Level Diagram
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Table 1 lists the ports and gives a description for each.
| Table 1. Signed Multiply-Adder Port Listing |
| Port Name |
Type |
Description |
dataa[15:0], datab[15:0], datac[15:0], datad[15:0] |
Input |
16-bit inputs to multiply-adder unit |
result[32:0] |
Output |
33-bit output of multiply-adder unit |
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