This example describes a single port 64-bit x 8-bit RAM design with common read and write addresses in Verilog HDL. Synthesis tools detect single clock synchronous RAM designs in HDL code and infer altsyncram or altdpram megafunctions depending on the target device architecture.
Figure 1. Single Port RAM Top-Level Diagram
***Graphic here (single-port-ram-vlog.gif)
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Table 1 lists the ports and gives a description for each.
| Table 1. Single Port RAM Port Listing | ||
| Port Name | Type | Description |
data[7:0] |
Input | 8-bit data input to RAM |
addr[5:0] |
Input | 6-bit address input to RAM |
we |
Input | Write enable input |
| clk | Input | Clock |
| q[7:0] | Output | 8-bit data output of RAM |
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