This design demonstrates a Stratix® IV device interfacing with 64-bit wide DDR3 SDRAM running at 400 MHz. The 64-bit DDR3 SDRAM interface comprises four MT41J64M16LA-187E DDR3 SDRAM components.
The design features advanced I/O timing, board trace models, and the SignalTap® II logic analyzer in Quartus® II software. It is mapped to the Stratix IV GX Development Kit.
A walkthrough of the process is described in Volume 6, Section I of the External Memory Interface Handbook (PDF). Please refer to the Using DDR3 SDRAM in Stratix III and Stratix IV devices chapter for the full design guidelines and flow.
This design includes Tcl files for:
- Board trace models for the Stratix IV GX Development Kit
- Example driver "output ports" virtual pin assignments
- Pin location assignments for the Stratix IV GX Development KitDDR 3 SDRAM Interface
Download the files used in this example:
- Download emi_ddr3_siv_readme.txt
- Download emi_ddr3_siv.zip
Related Links
- Stratix IV GX Audio Video Development Kit
- Volume 6, Section I of the External Memory Interface Handbook (PDF)
Design Examples Disclaimer
These design examples may only be used within Altera® devices and remain the property of Altera Corporation. They are being provided on an "as-is" basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
