Verilog HDL: Unsigned Multiplier
This example describes an 8-bit unsigned multiplier design in Verilog HDL. Synthesis tools detect multipliers in HDL code and infer lpm_mult megafunction.
Figure 1. Unsigned Multiplier Top-Level Diagram
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The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Table 1 lists the ports and gives a description for each.
| Table 1. Unsigned Multiplier Port Listing |
| Port Name |
Type |
Description |
a[7:0], b[7:0] |
Input |
8-bit data inputs to multiplier unit |
out[15:0] |
Output |
16-bit multiplier output |
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