Verilog HDL: Unsigned Multiply-Accumulator
This example describes an 8-bit unsigned multiply-accumulator design with registered I/O ports in Verilog HDL. Synthesis tools detect multiply-accumulator designs in HDL code and infer the altmult_accum megafunction.
Figure 1. Unsigned Multiply-Accumulator Top-Level Diagram
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The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Table 1 lists the ports and gives a description for each.
| Table 1. Unsigned Multiply-Accumulator Port Listing |
| Port Name |
Type |
Description |
dataa[7:0], datab[7:0] |
Input |
8-bit data inputs to multiply-accumulator unit |
clk |
Input |
Clock |
aclr |
Input |
Asynchronous clear |
clken |
Input |
Clock enable |
dataout[31:0] |
Output |
32-bit output of multiply-accumulator unit |
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