This example describes an 8-bit unsigned multiply-accumulator design with registered I/O ports and synchronous load in Verilog HDL. Synthesis tools detect multiply-accumulator designs in HDL code and infer the altmult_accum megafunction.
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Table 1 lists the ports and gives a description for each.
| Table 1. Unsigned Multiply-Accumulator Port Listing | ||
| Port Name | Type | Description |
dataa[7:0], datab[7:0] |
Input | 8-bit data inputs to multiply-accumulator unit |
clk |
Input | Clock |
aclr |
Input | Asynchronous clear |
clken |
Input | Clock enable |
| sload | Input | Synchronous load input |
adder_out[15:0] |
Output | 16-bit output of multiply-accumulator unit |
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