Verilog HDL: Basic IIR Filter
An infinite impulse response (IIR) filter is a recursive filter where the current output depends on previous outputs. The basic equation is shown below:
This is where n represents the order of the filter, and the ai and bi terms represent the coefficients of the filter, which consequently determine the filter characteristics. The feedback feature makes IIR filters useful in high-data throughput applications that require low hardware usage. However, the feedback adds complexity to the filter design as it introduces phase distortion and finite word length effects that may cause instability. Careful design consideration must be given to avoid unbounded conditions.
This becomes more critical as the filter order increases. To prevent overflow or instability, the transfer function is divided into second order filters called biquads. This is represented in the figure below as cascaded transfer functions.
These biquads can be individually scaled and cascaded, which minimizes quantization and recursive accumulation errors.
This IIR filter design uses two biquads to implement a fourth-order filter in Stratix™. The input is a 13-bit signed integer, the filter coefficients are scaled to 10 bits, and the output is 38 bits wide. For more details, see the Implementing High-Performance DSP Functions in Stratix & Stratix GX Devices chapter of the Stratix Device Handbook.
Download the files used in this example:
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Files in the download include:
- base_iir.v - Top-level design file
- base_iir_biquad.v - Second-order biquad structure
- four_mult_add.v - Multiply-add function implemented using altmult_add Megafunction
- two_mult_add.v - Multiply-add function implemented using altmult_add Megafunction
- adder.v - Adder to store the intermediate feedback values implemented using logic cells
- basic_iir.m - MATLAB script to verify functionality of design
Figure 1 contains the base_iir top-level block diagram.
Figure 1. base_iir Top-Level Block Diagram
Table 1 shows the basic IIR design example port listing.
| Table 1. Basic FIR Filter Design Example Port Listing |
| Port Name |
Type |
Description |
| x[12..0] |
Input |
The input is a 13-bit signed integer. This is the x[n] time sample represented as an 18?bit signed input. |
| clk |
Input |
Clock |
| clken |
Input |
Clock enable |
| reset |
Input |
Reset |
| result[37..0] |
Output |
Output of the IIR filter. This is 38 bits wide in the 24.14 signed binary fractional (SBF) format. |
For more information on using this example, go to:
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