Verilog HDL: Discrete Cosine Transform
Similar to discrete fourier transform (DFT), discrete cosine transform (DCT) is a function that maps the input signal or image from spatial domain to frequency domain. DCT transforms the input into a linear combination of weighted basis functions. These basis functions are the frequency component of the input data.
The two-dimensional DCT is just a one-dimensional DCT applied twice, once in the x direction, and again in the y direction. When you apply the DCT to an input image, it yields a matrix of weighted values corresponding to how much of each basis function is present in the original image. For most images, much of the signal energy lies at low frequencies; these appear in the upper-left corner of the DCT. The lower-right values represent higher frequencies, and are often small - small enough to be neglected with little visible distortion.
With an input image, x(m,n), the coefficients for the output image, Y(p,q), are:
This serial implementation of the 8x8 two-dimensional DCT design takes in an 8x8 input image with gray pixel values ranging from 0-255 (8-bit) and outputs an 8x8 output image transform. Appropriate scaling needs to be applied to the completed transform, but this can be combined with the quantization stage, which often follows a DCT.
For more details, see the Implementing High-Performance DSP Functions in Stratix & Stratix GX Devices chapter of the Stratix Device Handbook.
Download the files used in this example:
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Files in the download include:
- two_d_dct.v - Top-level design file
- row_dct.v - Process the data using one-dimensional DCT on a row-by-row basis
- column_dct.v - Process the data using one-dimensional DCT on a column-by-column basis
- transpose_matrix.v - Stores the partial transform from the row-processing stage, and reorders the data for the column-processing stage
- dct_2d.m - MATLAB script to verify the functionality of the design
Figure 1 contains the two_d_dct top-level block diagram.
Figure 1. two_d_dct Top-Level Block Diagram
Table 1 contains the DCT design example port listings.
| Table 1. DCT Design Example Port Listing |
| Port Name |
Type |
Description |
| serial_data[7..0] |
Input |
The input is an 8-bit unsigned pixel value from the 8x8 input image. Data is fed into the block serially starting from the top left pixel, moving horizontally on a row-by-row basis. |
| clk |
Input |
Clock |
| clken |
Input |
Clock enable. If clken is high, the function will start to calculate the discrete cosine transform based on the input serial data. This signal has to remain high throughout all 64-input data. |
| aclr |
Input |
Asynchronous clear |
| dct_out[21..0] |
Output |
The DCT output is in the 14:8 signed binary fractional format |
| data_valid |
Output |
Indicates the output is ready. The signal will remain high while all 64 outputs are piped out. |
For more information on using this example, go to:
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
|
文档资料
> 
