Verilog HDL: Polyphase Decimation FIR filter
In a polyphase decimation filter the output sample rate is 1/m times the input sample rate, with m being the decimation factor. Polyphase filters can simplify the overall design and reduce the number of computations needed. This document describes the implementation of a 16-tap, low-pass finite impulse response (FIR) filter using four polyphase decimation filters.
A single DSP block can implement up to four taps. By cycling the coefficients on every cycle of the 4x clock, it can implement the 16-tap FIR filter. The coefficient loading schedule is shown in Table 1. Input samples and data are loaded in parallel and can be up to 18 bits wide.
| Table 1. Coefficient Loading Schedule for Decimation Polyphase Filter |
| Cycle of 4x Clock |
Coefficients to be Loaded |
| 1, 5…… |
h(0), h(4), h(8), h(12) |
| 2, 6…… |
h(3), h(7), h(11), h(15) |
| 3, 7…… |
h(2), h(6), h(10), h(14) |
| 4, 8…… |
h(1), h(5), h(9), h(13) |
For more details, see the Implementing High-Performance DSP Functions in Stratix & Stratix GX Devices chapter of the Stratix Device Handbook.
Download the files used in this example:
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Files in the download include:
- deci_poly.v - Top-level design file
- pll.v - Phase-locked loop (PLL) to generate 1x and 4x clock
- shift_reg.v - Shift register implemented using altshift_taps megafunction
- mult_add.v - Multiply-add function implemented using altmult_add megafunction
- accumulator.v - Accumulator implemented using lpm_add_sub megafunction
- rom0.v, rom1.v, rom2.v, rom3.v - ROM blocks to store filter coefficients
- rom1.mif, rom1.mif, rom2.mif, rom3.mif - Memory initialization file for filter coefficients
- deci_poly.m - MATLAB script to verify functionality of design
Figure 1 contains the deci_poly top-level block diagram.
Figure 1. deci_poly Top-Level Block Diagram
Table 2 contains the polyphase decimation FIR filter example port listing.
| Table 2. Polyphase Decimation FIR Filter Design Example Port Listing |
| Port Name |
Type |
Description |
| x0[8..0] |
Input |
Signed 9-bit input data is shifted in serially using the shift register within the DSP block |
| clk |
Input |
Clock |
| clken |
Input |
Clock enable |
| reset |
Input |
Reset |
| load_data |
Output |
When asserted, the filter is ready to accept data on the x0 port |
| result[25..0] |
Output |
Output of the decimation FIR filter |
For more information on using this example, go to:
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
|
文档资料
> 
