Verilog HDL: Fully Variable Coefficient Soft Multiplier
This design implements 8-bit fully variable multiplication using M4K RAM blocks as look-up tables (LUTs). For more details on the design, refer to AN 306: Implementing Multipliers in FPGA Devices.
Download the file(s) used in this example:
Table 1 shows the Fully Variable Coefficient Soft Multiplier design example port listing.
|
Table 1. Fully Variable Coefficient Soft Multiplier Port Listing
|
|
Port Name
|
Type
|
Description
|
|
data_a[7..0]
|
Input
|
8-bit unsigned input to the multiplier. New input can be sent to the multiplier every clock cycle.
|
|
data_b[7..0]
|
Input
|
8-bit unsigned input to the multiplier. New input can be sent to the multiplier every clock cycle.
|
|
clk
|
Input
|
Clock
|
|
sclr
|
Input
|
Active high synchronous clear
|
|
result[15..0]
|
Output
|
The output is a 32-bit unsigned value.
|
For more information on using this example in your project, go to:
Feedback
Did this information help you?
If not, please log onto mySupport to file a technical request or enhancement.
Altera does not warrant that this example will work for the customer's intended purpose and disclaims all liability for use of or reliance on the example.
|
文档资料
> 
