Verilog HDL: Creating a Hierarchical Design
This example describes how to create a hierarchical design using Verilog HDL. This design is identical to the VHDL, AHDL and schematic hierarchy examples. The file top_ver.v is the top level, which calls the two lower level files bottom1.v and bottom2.v.
For more information on using this example in your project, go to:
vprim.v
top_ver.v
module top_ver (q, p, r, out);
input q, p, r;
output out;
reg out, intsig;
bottom1 u1(.a(q), .b(p), .c(intsig));
bottom2 u2(.l(intsig), .m(r), .n(out));
endmodule
bottom1.v
module bottom1(a, b, c);
input a, b;
output c;
reg c;
always
begin
c<=a & b; end endmodule </pre>
bottom2.v
module bottom2(l, m, n);
input l, m;
output n;
reg n;
always
begin
n<=l | m; end endmodule </pre>
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
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