Verilog HDL: Magnitude
For a vector (a,b), the magnitude representation is the following:
A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm.
This design example calculates the magnitude of a 9-bit signed vector (a,b) using a pipelined square root function. To calculate the sum of the squares of the input (a2 + b2), the DSP block can be configured in the Two-Multipliers Adder mode. The square root function is implemented using an iterative algorithm, which is similar to the long division operation. The binary numbers are paired off, and subtracted by a trial number. Depending if the remainder is positive or negative, each bit of the square root is determined and the process is repeated. This square root function does not require memory and is implemented in logic cells only.
In this example, the output precision of the square root function is set to 10. It is possible to increase the precision of the output but this will increase the utilization of logic cells. For more details, see the Implementing High-Performance DSP Functions in Stratix & Stratix GX Devices chapter of the Stratix Device Handbook.
For more information on the square root function, please refer to the Altera IP MegaStoreTM.
A license is required in order for this design example to work properly. For more information, please refer to the README file.
Download the files used in this example:
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Files in the download include:
- magnitude.v - Top-level design file
- square_numbers.tdf - Calculates the sum of squares of the input using DSP blocks
- root_pipeline_wrapper.tdf - Pipelined version of the square root macro
Before you can use the design example, you must copy and paste the license information
from the file sqroot_license.txt into your license file for the Quartus II software.
Figure 1 shows the Magnitude top-level block diagram.
Figure 1. Magnitude Top-Level Block Diagram
Table 1 contains a listing of Magnitude design example ports and parameters.
| Table 1. Magnitude Design Example Port & Parameter Listing |
| Port Name |
Type |
Description |
vectorX[8..0]
vectorY[8..0] |
Input |
The input is a 9-bit signed vector |
| clk |
Input |
Clock |
| clken |
Input |
Clock enable |
| aclr |
Input |
Asynchronous clear |
| magnitude[9..0] |
Output |
If clken is high, the function will calculate the magnitude based on the input vectorX, and vectorY. Otherwise, it will remain idle. |
| Parameter |
Type |
Description |
| IN_PREC |
Integer |
Input bit precision feeding into the square root macro |
| OUT_PREC |
Integer |
Output bit precision from the square root macro |
| PIPELINE |
String |
This parameter controls the architecture of the square root macro. If set to "YES", it includes pipeline stages in the square root macro. If set to "NO", the square root macro becomes a single-cycle combinatorial function. |
For more information on using this example, go to:
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