Verilog HDL: Parallel Fixed Coefficient Soft Multiplier
This design implements 16-bit input, 10-bit fixed coefficient parallel multiplication using M4K RAM blocks as look-up tables (LUTs). For more details on the design, refer to AN 306: Implementing Multipliers in FPGA Devices (PDF).
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Table 1 shows the Parallel Fixed Soft Multiplier design example port listing.
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Table 1. Parallel Fixed Soft Multiplier Port Listing
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Port Name
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Type
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Description
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data_in[15..0]
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Input
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The input is a 16-bit signed value. New data can be sent to the multiplier once every clock cycle.
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clock
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Input
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Clock
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sclr
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Input
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Active high synchronous clear
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result[25..0]
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Output
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The output is a 26-bit signed value. New value is available on the output once every clock cycle.
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