Verilog HDL: Parallel Variable Coefficient Soft Multiplier
This design implements 16-bit input, 10-bit variable coefficient parallel multiplication using M4K RAM blocks as look-up tables (LUTs). For more details on the design, refer to AN 306: Implementing Multipliers in FPGA Devices (PDF).
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The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Table 1 shows the Parallel Variable Soft Multiplier design example port listing.
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Table 1. Parallel Variable Soft Multiplier Port Listing
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Port Name
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Type
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Description
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data_in[15..0]
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Input
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The input is a 16-bit signed value. New data can be sent to the multiplier once every clock cycle.
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lsb_coef_in[17:0]
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Input
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Coefficient update port for LSB input bits. Pre-calculated coefficient values on this port will be stored in to locations specified by coef_add_in when the coef_wren signal is enabled.
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msb_coef_in[17:0]
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Input
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Coefficient update port for MSB input bits. Pre-calculated coefficient values on this port will be stored in to locations specified by coef_add_in when the coef_wren signal is enabled.
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coef_add_in[7:0]
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Input
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Coefficient update address port. This specifies which address location a particular pre-calculated coefficient value is written to. This port feeds both the LSB and MSB RAM blocks so the LSB and MSB coefficients can be updated at the same time.
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coef_wren
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Input
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Coefficient write/update enable. If coef_wren is high, the RAM blocks will start to accept pre-calculated coefficient values on the lsb_coef_in and msb_coef_in signals and store them in the locations specified by the coef_add_in signal. This signal has to remain high till all the pre-calculated coefficient values have been updated in the RAM blocks.
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clock
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Input
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Clock
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clr
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Input
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Active high synchronous clear
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result[25..0]
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Output
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The output is a 26-bit signed value. New value is available on the output once every clock cycle.
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