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Verilog HDL: Parallel Variable Coefficient Soft Multiplier

This design implements 16-bit input, 10-bit variable coefficient parallel multiplication using M4K RAM blocks as look-up tables (LUTs). For more details on the design, refer to AN 306: Implementing Multipliers in FPGA Devices (PDF).

Download the file(s) used in this example:

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

Table 1 shows the Parallel Variable Soft Multiplier design example port listing.

Table 1. Parallel Variable Soft Multiplier Port Listing

Port Name

Type

Description

data_in[15..0]

Input

The input is a 16-bit signed value. New data can be sent to the multiplier once every clock cycle.

lsb_coef_in[17:0]

Input

Coefficient update port for LSB input bits. Pre-calculated coefficient values on this port will be stored in to locations specified by coef_add_in when the coef_wren signal is enabled.

msb_coef_in[17:0]

Input

Coefficient update port for MSB input bits. Pre-calculated coefficient values on this port will be stored in to locations specified by coef_add_in when the coef_wren signal is enabled.

coef_add_in[7:0]

Input

Coefficient update address port. This specifies which address location a particular pre-calculated coefficient value is written to. This port feeds both the LSB and MSB RAM blocks so the LSB and MSB coefficients can be updated at the same time.

coef_wren

Input

Coefficient write/update enable. If coef_wren is high, the RAM blocks will start to accept pre-calculated coefficient values on the lsb_coef_in and msb_coef_in signals and store them in the locations specified by the coef_add_in signal. This signal has to remain high till all the pre-calculated coefficient values have been updated in the RAM blocks.

clock

Input

Clock

clr

Input

Active high synchronous clear

result[25..0]

Output

The output is a 26-bit signed value. New value is available on the output once every clock cycle.

For more information on using this example in your project, go to:

Design Examples Disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.

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